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rev. 1.8 october 2001 1/132 st72141k 8-bit mcu with electric-motor control, adc, 16-bit timers, spi interface n memories C 8k program memory (rom/otp/eprom) C 256 bytes ram n clock, reset and supply management C enhanced reset system C low voltage supply supervisor C 3 power saving modes n 14 i/o ports C 14 multifunctional bidirectional i/o lines with: external interrupt capability (2 vectors), 13 al- ternate function lines, 3 high sink outputs n motor control peripheral C 6 pwm output channels C emergency pin to force outputs to hiz state C 3 analog inputs for rotor position detection with no need for additional sensors C comparator for current limitation n 3 timers C two 16-bit timers with: 2 input captures, 2 out- put compares, external clock input, pwm and pulse generator modes C watchdog timer for system integrity n communications interface C spi synchronous serial interface n analog peripheral C 8-bit adc with 8 input pins n instruction set C 8-bit data manipulation C 63 basic instructions C 17 main addressing modes C 8 x 8 unsigned multiply instruction C true bit manipulation n development tools C full hardware/software development package device summary sdip32 so34s features st72141k2 program memory - bytes 8k ram (stack) - bytes 256 (64) peripherals motor control, watchdog, two 16-bit timers, spi, adc operating supply 4v to 5.5v cpu frequency 4 or 8 mhz (with 8 or 16 mhz oscillator) operating temperature -40c to +85c / -40c to +125c packages so34 / sdip32 1
table of contents 132 2/132 2 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 eprom program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 reset manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 3.3 low consumption oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 main clock controller (mcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.1 input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.2 output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.3 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3.1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1 i/o port interrupt sensitivity description . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2 i/o port alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.3 clock prescaler selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4 miscellaneous register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1 motor controller (mtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 8.1.3 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
table of contents 3/132 3 8.1.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.1.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.1.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.2 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.2.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 8.2.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.2.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.2.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.2.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 8.3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.3.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.3.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.3.6 summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.3.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 8.4.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.4.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.4.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.4.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.4.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.5 8-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.5.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.5.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.5.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.1.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.1.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 13 9.1.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.1.4 indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.1.5 indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.1.6 indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.1.7 relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 10.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 10.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
table of contents 132 4/132 10.4 general timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10.6 supply, reset and clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.6.1supply manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.6.2reset s equence manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.6.3clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1 10.7 memory and peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 11 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 11.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 11.2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 12 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 1
st72141k 5/132 1 general description 1.1 introduction the st72141k devices are members of the st7 microcontroller family designed specifically for mo- tor control applications and including a/d conver- sion and spi interface capabilities. they include an on-chip moter controller peripheral for control of electric brushless moters with or without sen- sors. an example application, for 6-step control of a permanent magnet dc motor, is shown in figure 1 . the st72141k devices are based on a common industry-standard 8-bit core, featuring an en- hanced instruction set. under software control, they can be placed in wait, slow, or halt mode, reducing power consumption when the application is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. figure 1. example of a 6-step-controlled motor figure 2. device block diagram 0 1 2 3 4 5 a b c net step s 1 s 2 s 3 s 4 s 5 s 6 s 1 s 2 s 3 c a b 300v 4 1 i 4 i 1 i 3 i 6 i 2 i 5 300v 150v 0 300v 150v 0 300v 150v 0 st7 mtc mco5- 0 mci b mci a mci c 2 0 3 5 6 8-bit core alu address and data bus osc1 osc2 reset motor ctrl timer b timer a port b watchdog mco5:0 osc internal clock control 256b-ram pa7:0 v ss v dd power supply 8k-eprom port a 8-bit adc spi oc1a mcia:c mces mccfi pb5:0 div lvd (6-bit) (8-bit) 4
st72141k 6/132 1.2 pin description figure 3. 34-pin so package pinout figure 4. 32-pin sdip package pinout 18 19 20 21 22 23 31 30 29 28 27 26 25 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 mco5 mco4 extclk_a/ (hs) pb0 extclk_b/ (hs) pb1 ss / (hs) pb2 sck/pb3 mosi/pb4 nc miso/pb5 mces mco0 mco1 mco2 mco3 mccfi v dd pa0/ain0 pa1/ain1/icap2_b pa2/ain2/icap1_b pa3/ain3/ocmp2_b pa4/ain4/ocmp1_b pa5/ain5/icap2_a pa6/ain6/icap1_a pa7/ain7/ocmp2_a nc ocmp1_a v pp v ss ei1 ei0 15 16 17 reset osc2 osc1 34 33 32 mcia mcib mcic 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 29 30 31 32 mco5 mco4 reset osc2 osc1 extclk_a/ (hs) pb0 extclk_b/ (hs) pb1 ss / (hs) pb2 sck/pb3 mces mco0 mco1 mco2 mco3 mosi/pb4 miso/pb5 mcia mcib pa0/ain0 pa1/ain1/icap2_b pa2/ain2/icap1_b pa3/ain3/ocmp2_b pa4/ain4/ocmp1_b pa5/ain5/icap2_a pa6/ain6/icap1_a v pp v ss v dd mccfi mcic ocmp1_a pa7/ain7/ocmp2_a ei1 ei0 5
st72141k 7/132 pin description (contd) legend / abbreviations: type: i = input, o = output, s = supply input level: a = dedicated analog input in/output level: c = cmos 0.3v dd /0.7v dd , c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = high sink (on n-buffer only), r = 70 w /100 w ratio of logical levels. analog level if used as pwm filtered with an external capacitor port configuration capabilities: C input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog C output: od = open drain, t = true open drain, pp = push-pull note: the reset configuration of each pin is shown in bold. table 1. device pin description pin n pin name type level port / control main function (after reset) alternate function sdip32 so34 input output input output float wpu int ana od pp 1 1 mco5 o c x motor control output channel 5 2 2 mco4 o c x motor control output channel 4 3 3 mco3 o c x motor control output channel 3 4 4 mco2 o c x motor control output channel 2 5 5 mco1 o c x motor control output channel 1 6 6 mco0 o c x motor control output channel 0 7 7 mces ic t x motor control emergency stop input 8 8 pb5/miso i/o c t x ei1 x x port b5 spi master in / slave out data 9 nc not connected 9 10 pb4/mosi i/o c t x ei1 x x port b4 spi master out / slave in data 10 11 pb3/sck i/o c t x ei1 x x port b3 spi serial clock 11 12 pb2/ss i/o c t hs x ei1 t port b2 spi slave select (active low) 12 13 pb1/extclk_b i/o c t hs x ei1 t port b1 timer b input clock 13 14 pb0/extclk_a i/o c t hs x ei1 t port b0 timer a input clock 14 15 osc1 these pins connect a crystal or ceramic resonator, or an external rc, or an external source to the on-chip oscillator 15 16 osc2 16 17 reset i/o c x x top priority non maskable interrupt (active low) 17 18 pa0/ain0 i/o c t x ei0 x x x port a0 adc analog input 0 18 19 pa1/icap2_b/ain1 i/o c t x ei0 x x x port a1 timer b input capture 2 or adc analog input 1 19 20 pa2/icap1_b/ain2 i/o c t x ei0 x x x port a2 timer b input capture 1 or adc analog input 2 6
st72141k 8/132 20 21 pa3/ocmp2_b/ain3 i/o c t x ei0 x x x port a3 timer b output compare 2 or adc analog input 3 21 22 pa4/ocmp1_b/ain4 i/o c t x ei0 x x x port a4 timer b output compare 1 or adc analog input 4 22 23 pa5/icap2_a/ain5 i/o c t x ei0 x x x port a5 timer a input capture 2 or adc analog input 5 23 24 pa6/icap1_a/ain6 i/o c t x ei0 x x x port a6 timer a input capture 1 or adc analog input 6 24 25 pa7/ocmp2_a/ain7 i/o c t x ei0 x x x port a7 timer a output compare 2 or adc analog input 7 26 nc not connected 25 27 ocmp1_a o r timer a output compare 1 26 28 v pp i must be tied low during normal operating mode,eprom programming voltage pin. 27 29 v ss s ground 28 30 v dd s main power supply 29 31 mccfi i a motor control current feedback input 30 32 mcic i a motor control input c 31 33 mcib i a motor control input b 32 34 mcia i a motor control input a pin n pin name type level port / control main function (after reset) alternate function sdip32 so34 input output input output float wpu int ana od pp
st72141k 9/132 1.3 external connections the following figure shows the recommended ex- ternal connections for the device. the v pp pin is only used for programming otp and eprom devices and must be tied to ground in user mode. the 10 nf and 0.1 f decoupling capacitors on the power supply lines are a suggested emc per- formance/cost tradeoff. the external reset network is intended to protect the device against parasitic resets, especially in noisy environments. unused i/os should be tied high to avoid any un- necessary power consumption on floating lines. an alternative solution is to program the unused ports as inputs with pull-up. figure 5. recommended external connections v pp v dd v ss osc1 osc2 reset v dd 0.1f + see clocks section v dd 0.1f 0.1f external reset circuit or configure unused i/o ports unused i/o 10f 4.7k 10k by software as input with pull-up v dd detector (lvd) is used optional if low voltage v dd v ss
st72141k 10/132 1.4 register & memory map as shown in figure 6 , the mcu is capable of ad- dressing 64k bytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, 256 bytes of ram and 8kbytes of user program memory. the ram space includes up to 64 bytes for the stack from 0140h to 017fh. the highest address bytes contain the user reset and interrupt vectors. figure 6. memory map table 2. interrupt vector map 0000h program memory (8k bytes) interrupt & reset vectors hw registers dfffh 0080h 007fh (see table 3 ) e000h ffdfh ffe0h ffffh (see table 2 ) 0180h reserved 017fh short addressing ram 16-bit addressing 0100h 013fh 0080h 00ffh 256 bytes ram ram stack or 16-bit addressing 0140h 017fh ram (64 bytes) zero page (64 bytes) (128 bytes) vector address description remarks ffe0-ffe1h ffe2-ffe3h ffe4-ffe5h ffe6-ffe7h ffe8-ffe9h ffea-ffebh ffec-ffedh ffee-ffefh fff0-fff1h fff2-fff3h fff4-fff5h fff6-fff7h fff8-fff9h fffa-fffbh fffc-fffdh fffe-ffffh not used not used not used not used not used timer b interrupt vector timer a interrupt vector spi interrupt vector motor control interrupt vector (events: e, o) motor control interrupt vector (events: c, d) motor control interrupt vector (events: r, z) external interrupt vector ei1: port b7..0 external interrupt vector ei0: port a7..0 not used trap (software) interrupt vector reset vector internal interrupt external interrupt external interrupt cpu interrupt
st72141k 11/132 table 3. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a padr paddr paor port a data register port a data direction register port a option register 00h 00h 00h r/w r/w r/w 0003h reserved area (1 byte) 0004h 0005h 0006h port b pbdr pbddr pbor port b data register port b data direction register port b option register 00h 00h 00h r/w r/w r/w. 0007h to 001f reserved area (24 byte) 0020h miscr miscellaneous register 00h r/w 0021h 0022h 0023h spi spidr spicr spisr spi data i/o register spi control register spi status register xxh 0xh 00h r/w r/w read only 0024h 0025h watchdog wdgcr wdgsr watchdog control register watchdog status register 7fh x0h r/w read only 0026h to 0030h reserved area (11 bytes) 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a tacr2 tacr1 tasr taic1hr taic1lr taoc1hr taoc1lr tachr taclr taachr taaclr taic2hr taic2lr taoc2hr taoc2lr timer a control register 2 timer a control register 1 timer a status register timer a input capture 1 high register timer a input capture 1 low register timer a output compare 1 high register timer a output compare 1 low register timer a counter high register timer a counter low register timer a alternate counter high register timer a alternate counter low register timer a input capture 2 high register timer a input capture 2 low register timer a output compare 2 high register timer a output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0040h reserved area (1 byte)
st72141k 12/132 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b tbcr2 tbcr1 tbsr tbic1hr tbic1lr tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic2hr tbic2lr tboc2hr tboc2lr timer b control register 2 timer b control register 1 timer b status register timer b input capture 1 high register timer b input capture 1 low register timer b output compare 1 high register timer b output compare 1 low register timer b counter high register timer b counter low register timer b alternate counter high register timer b alternate counter low register timer b input capture 2 high register timer b input capture 2 low register timer b output compare 2 high register timer b output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h to 005fh reserved area (16 bytes) 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh motor control mtim mzprv mzreg mcomp mdreg mwght mprsr mimr misr mcra mcrb mphst mpar mpol timer counter register zn-1 capture register zn capture register c n+1 compare register d capture/compare register weight register prescaler and ratio register interrupt mask register interrupt status register control register a control register b phase state register output parity register output polarity register 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 006eh to 006fh reserved area (2 bytes) 0070h 0071h adc adcdr adccsr data register control/status register 00h 00h read only r/w 0072h to 007fh reserved area (14 bytes) address block register label register name reset status remarks
st72141k 13/132 1.5 eprom program memory the program memory of the otp and eprom de- vices can be programmed with eprom program- ming tools available from stmicroelectronics. eprom erasure eprom devices are erased by exposure to high intensity uv light admitted through the transparent window. this exposure discharges the floating gate to its initial state through induced photo cur- rent. it is recommended that the eprom devices be kept out of direct sunlight, since the uv content of sunlight can be sufficient to cause functional fail- ure. extended exposure to room level fluorescent lighting may also cause erasure. an opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting con- ditions. covering the window also reduces i dd in power-saving modes due to photo-diode leakage currents.
st72141k 14/132 2 central processing unit 2.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 main features n 63 basic instructions n fast 8-bit by 8-bit multiply n 17 main addressing modes n two 8-bit index registers n 16-bit stack pointer n low power modes n maskable hardware interrupts n non-maskable software interrupt 2.3 cpu registers the 6 cpu registers shown in figure 7 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede in- struction (pre) to indicate that the following in- struction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 7. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value
st72141k 15/132 cpu registers (contd) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 3 = i interrupt mask . this bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret in- structions and is tested by the jrm and jrnm in- structions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptable because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the bit test and branch, shift and rotate instructions. 70 111hinzc
st72141k 16/132 central processing unit (contd) stack pointer (sp) read/write reset value: 01 7fh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 8 ). since the stack is 128 bytes deep, the 9th most significant bits are forced by hardware. following an mcu reset, or after a reset stack pointer in- struction (rsp), the stack pointer contains its re- set value (the sp6 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 8 . C when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. C on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. figure 8. stack manipulation example 15 8 00000001 70 0 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 017fh @ 0100h stack higher address = 017fh stack lower address = 0100h
st72141k 17/132 3 supply, reset and clock management the st72141k includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. an overview is shown in figure 9 . main features n main supply low voltage detection (lvd) n reset m anager n low consumption resonator oscillator n main clock controller (mcc) figure 9. clock, reset, option and supply management overview f osc main clock controller (mcc) low voltage detector (lvd) f cpu from watchdog peripheral osc2 osc1 reset v dd v ss f motor_control oscillator reset f spi
st72141k 18/132 3.1 low voltage detector (lvd) to allow the integration of power management features in the application, the low voltage detec- tor function (lvd) generates a static reset when the v dd supply voltage is below a v lvdf reference value. this means that it secures the power-up as well as the power-down keeping the st7 in reset. the v lvdf reference value for a voltage drop is lower than the v lvdr reference value for power-on in order to avoid a parasitic reset when the mcu starts running and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: Cv lvdr when v dd is rising Cv lvdf when v dd is falling the lvd function is illustrated in figure 10 . provided the minimum v dd value (guaranteed for the oscillator frequency) is below v lvdf , the mcu can only be in two modes: C under full software control C in static safe reset in these conditions, secure operation is always en- sured for the application without the need for ex- ternal reset hardware. during a low voltage detector reset, the r eset pin is held low, thus permitting the mcu to reset other devices. notes : the lvd allows the device to be used without any external reset circuitry. figure 10. low voltage detector vs reset v dd v lvdr reset v lvdf hysterisis v lvdhyst
st72141k 19/132 3.2 reset manager the reset block includes three reset sources as shown in figure 11 : n external reset source pulse n internal lvd reset (low voltage detection) n internal watchdog reset the reset service routine vector is fixed at ad- dresses fffeh-ffffh in the st7 memory map. a 4096 cpu clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the reset state. the reset vector fetch phase duration is 2 clock cycles. figure 11. reset block diagram f cpu counter reset r on v dd watchdog reset lvd reset internal reset
st72141k 20/132 reset manager (contd) external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor (see figure 11 ). this pull-up has no fixed value but varies in accordance with the input voltage. it can be pulled low by external circuitry to reset the de- vice. a reset signal originating from an external source must have a duration of at least t pulse in order to be recognized. two reset sequences can be associated with this reset source as shown in figure 12 . when the r eset is generated by a internal source, during the two first phases of the reset sequence, the device reset pin acts as an out- put that is pulled low. generic power on reset the function of the por circuit consists of waking up the mcu by detecting (at around 2v) a dynamic (rising edge) variation of the v dd supply. at the beginning of this sequence, the mcu is configured in the reset state. when the power supply volt- age rises to a sufficient level, the oscillator starts to operate, whereupon an internal 4096 cpu cycles delay is initiated, in order to allow the oscillator to fully stabilize before executing the first instruction. the initialization sequence is executed immediate- ly following the internal delay. to ensure correct start-up, the user should take care that the vdd supply is stabilized at a suffi- cient level for the chosen frequency (see electrical characteristics) before the reset signal is re- leased. in addition, supply rising must start from 0v. as a consequence, the por does not allow to su- pervise static, slowly rising, or falling, or noisy (os- cillating) v dd supplies. an external rc network connected to the r eset pin, or the lvd reset can be used instead to get the best performance. figure 12. external reset sequences reset run internal reset 4096 clock cycles fetch vector run reset pin external reset source t pulse v dd v lvdf v dd nominal watchdog reset delay
st72141k 21/132 reset manager (contd) internal low voltage detection reset (option) two different reset sequences caused by the in- ternal lvd circuitry can be distinguished: - lvd power-on reset - voltage drop reset in the second sequence, a delay phase is used to keep the device in reset state until v dd rises up to v lvdr (see figure 13 ). figure 13. lvd reset sequences reset run internal reset 4096 clock cycles fetch vector power- reset pin external reset source watchdog reset reset run internal reset 4096 clock cycles fetch vector run reset pin external reset source v dd v ddnominal watchdog reset delay v lvdr v lvdf v dd v ddnominal v lvdr lvd power-on reset voltage drop reset off
st72141k 22/132 reset manager (contd) internal watchdog reset the reset s equence generated by a internal watchdog counter overflow has the shortest reset phase (see figure 14 ). figure 14. watchdog reset sequence reset run internal reset 4096 clock cycles fetch vector run reset pin external reset source v dd v lvdf v ddnominal watchdog reset watchdog underflow t wdgrst
st72141k 23/132 3.3 low consumption oscillator the main clock of the st7 can be generated by two different sources: n an external source n a crystal or ceramic resonator oscillators external clock source in this mode, a square clock signal with ~50% duty cycle has to drive the osc2 pin while the osc1 pin is tied to v ss (see figure 15 ). figure 15. external clock crystal/ceramic oscillators this oscillator (based on constant current source) is optimized in terms of consumption and has the advantage of producing a very accurate rate on the main clock of the st7. when using this oscillator, the resonator and the load capacitances have to be connected as shown in figure 16 and have to be mounted as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. this oscillator is not stopped during the r eset phase to avoid losing time in the oscillator start-up phase. figure 16. crystal/ceramic resonator osc1 osc2 external st7 source osc1 osc2 load capacitances st7 c l1 c l0
st72141k 24/132 3.4 main clock controller (mcc) the mcc block supplies the clock for the st7 cpu and its internal peripherals. it allows the slow power saving mode and the motor contral and spi peripheral clocks to be managed inde- pendently. the mcc functionality is controlled by two bits of the miscr register: sms and xt16. the xt16 bit acts on the clock of the motor control and spi peripherals while the sms bit acts on the cpu and the other peripherals. figure 17. main clock controller (mcc) block diagram div 2 sms - - cpu clock miscr to cpu and peripherals f osc f cpu osc2 osc1 - - - - xt16 oscillator mcc div 16 4mhz motor control peripheral div 2 4mhz spi peripheral div 2
st72141k 25/132 4 interrupts the st7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the interrupt mapping table and a non- maskable software interrupt (trap). the interrupt processing flowchart is shown in figure 18 . the maskable interrupts must be enabled by clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). note: after reset, all interrupts are disabled. when an interrupt has to be serviced: C normal processing is suspended at the end of the current instruction execution. C the pc, x, a and cc registers are saved onto the stack. C the i bit of the cc register is set to prevent addi- tional interrupts. C the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the interrupt mapping table for vector address- es). the interrupt service routine should finish with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit will be cleared and the main program will resume. priority management by default, a servicing interrupt cannot be inter- rupted because the i bit is set by hardware enter- ing in interrupt routine. in the case when several interrupts are simultane- ously pending, an hardware priority defines which one will be serviced first (see the interrupt map- ping table). interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specifi- cally mentioned interrupts allow the processor to leave the halt low power mode (refer to the exit from halt column in the interrupt mapping ta- ble). 4.1 non maskable software interrupt this interrupt is entered when the trap instruc- tion is executed regardless of the state of the i bit. it will be serviced according to the flowchart on figure 18 . 4.2 external interrupts external interrupt vectors can be loaded into the pc register if the corresponding external interrupt occurred and if the i bit is cleared. these interrupts allow the processor to leave the halt low power mode. the external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). an external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins, connected to the same inter- rupt vector, are configured as interrupts, their sig- nals are logically nanded before entering the edge/level detection block. caution: the type of sensitivity defined in the mis- cellaneous or interrupt register (if available) ap- plies to the ei source. in case of a nanded source (as described on the i/o ports section), a low level on an i/o pin configured as input with interrupt, masks the interrupt request even in case of rising- edge sensitivity. 4.3 peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: C the i bit of the cc register is cleared. C the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by: C writing 0 to the corresponding bit in the status register or C access to the status register while the flag is set followed by a read or write of an associated reg- ister. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being en- abled) will therefore be lost if the clear sequence is executed.
st72141k 26/132 interrupts (contd) figure 18. interrupt processing flowchart i bit set? y n iret? y n from reset load pc from interrupt vector stack pc, x, a, cc set i bit fetch next instruction execute instruction this clears i bit by default restore pc, x, a, cc from stack interrupt y n pending?
st72141k 27/132 interrupts (contd) table 4. interrupt mapping n source block description register label priority order exit from halt address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 not used fffah-fffbh 1 ei0 external interrupt port a7..0 (c5..0*) n/a yes fffah-fffbh 2 ei1 external interrupt port b7..0 (c5..0*) yes fff8h-fff9h 3 mtc motor control interrupt (events: r, z) misr no fff4h-fff5h 4 motor control interrupt (events: c, d) no fff2h-fff3h 5 motor control interrupt (events: e, o) no fff0h-fff1h 6 spi spi peripheral interrupts spisr no ffeeh-ffefh 7 timer a timer a peripheral interrupts tasr no ffech-ffedh 8 timer b timer b peripheral interrupts tbsr no ffeah-ffebh 9 not used ffe8h-ffe9h 10 not used ffe6h-ffe7h 11 not used ffe4h-ffe5h 12 not used ffe2h-ffe3h 13 not used ffe0h-ffe1h
st72141k 28/132 5 power saving modes 5.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, three main power saving modes are implemented in the st7 (see figure 19 ). after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f cpu ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instruction whose action depends on the the oscil- lator status. figure 19. power saving mode consumption / transitions power consumption wait slow run halt high low slow wait
st72141k 29/132 power saving modes (contd) 5.2 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the st7 halt instruction (see figure 21 ). the mcu can exit halt mode on reception of ei- ther an external interrupt or a reset (see table 2 ). when exiting halt mode by means of a reset or an interrupt, the oscillator is immediately turned on and the 4096 cpu cycle delay is used to stabi- lize the oscillator. after the start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see fig- ure 20 ). when entering halt mode, the i bit in the cc register is forced to 0 to enable interrupts. in the halt mode the main oscillator is turned off causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla- tor). figure 20. halt mode timing overview figure 21. halt modes flow-chart halt run run 4096 cpu cycle delay reset or interrupt halt instruction fetch vector halt instruction notes: cpu oscillator peripherals i bit off off 0 off reset external* y n n y cpu oscillator peripherals on off off interrupt halt fetch reset vector or service interrupt** 4096 clock cycles delay cpu oscillator peripherals on on on external interrupt or internal interrupts with exit from halt mode capability * ** before servicing an interrupt, the cc register is pushed on the stack. watchdog y n enable
st72141k 30/132 power saving modes (contd) 5.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the wfi st7 software instruction. all peripherals remain active. during wait mode, the i bit of the cc register are forced to 0, to ena- ble all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereup- on the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 22 . 5.4 slow mode this mode has two targets: C to reduce power consumption by decreasing the internal clock in the device, C to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by the sms bit in the miscr register. this bit enables or disables slow mode selecting the internal slow frequency (f cpu ). in this mode, the oscillator frequency can be divid- ed by 32 instead of 2 in normal operating mode. the cpu and peripherals are clocked at this lower frequency except the motor control and the spi peripherals which have their own clock selection bit (xt16) in the miscr register. figure 22. wait mode flow-chart wfi instruction reset interrupt y n n y cpu oscillator peripherals i bit on on 0 off if exit caused by a reset, a 4096 cpu clock cycle delay is inserted. cpu oscillator peripherals on off* off note: * the peripheral clock is stopped only when exit caused by reset and not by an interrupt. ** before servicing an interrupt, the cc register is pushed on the stack. fetch reset vector or service interrupt** cpu oscillator peripherals on on on
st72141k 31/132 6 i/o ports 6.1 introduction the i/o ports offer different functional modes: C transfer of data through digital inputs and outputs and for specific pins: C external interrupt generation C alternate signal input/output for the on-chip pe- ripherals. an i/o port contains up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 6.2 functional description each port has 2 main registers: C data register (dr) C data direction register (ddr) and one optional register: C option register (or) each i/o pin may be programmed using the corre- sponding register bits in the ddr and or regis- ters: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not pro- vide this register refer to the i/o port implementa- tion section). the generic i/o block diagram is shown in figure 23 6.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. notes : 1. writing the dr register modifies the latch value but does not affect the pin status. 2. when switching from input to output mode, the dr register has to be written first to drive the cor- rect level on the pin as soon as the port is config- ured as an output. external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external inter- rupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the mis- cellaneous register. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see pinout description and interrupt section). if several input pins are se- lected simultaneously as interrupt source, these are logically nanded. for this reason if one of the interrupt pins is tied low, it masks the other ones. in case of a floating input with interrupt configura- tion, special care must be taken when changing the configuration (see figure 24 ). the external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. to clear an unwanted pending interrupt by software, the sensitivity bits in the miscellane- ous register must be modified. 6.2.2 output modes the output configuration is selected by setting the corresponding ddr register bit. in this case, writ- ing the dr register applies this digital value to the i/o pin through the latch. then reading the dr reg- ister returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. dr register value and output pin status: 6.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over the standard i/o programming. when the signal is coming from an on-chip periph- eral, the i/o pin is automatically configured in out- put mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin must be configured in input mode. in this case, the pin state is also digitally readable by addressing the dr register. note : input pull-up configuration can cause unex- pected value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as in- put and output, this pin has to be configured in in- put floating mode. dr push-pull open-drain 0v ss vss 1v dd floating
st72141k 32/132 i/o ports (contd) figure 23. i/o port general block diagram table 5. i/o port mode options legend : ni - not implemented off - implemented not activated on - implemented and activated note : the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ss is implemented to protect the de- vice against positive stress. configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (see note) dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up configuration p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external source (ei x ) interrupt polarity selection cmos schmitt trigger register access
st72141k 33/132 i/o ports (contd) table 6. i/o port configurations notes: 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read the alternate function output status. 2. when the i/o port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the dr register content. hardware configuration input 1) open-drain output 2) push-pull output 2) configuration pad v dd r pu external interrupt polarity data bus pull-up interrupt dr register access w r from other pins source (ei x ) selection dr register configuration alternate input not implemented in true open drain i/o ports analog input pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports
st72141k 34/132 i/o ports (contd) caution : the alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the select- ed pin to the common analog rail which is connect- ed to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning : the analog input voltage level must be within the limits stated in the absolute maxi- mum ratings. 6.3 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr and or registers and specific feature of the i/o port such as adc in- put or true open drain. switching these i/o ports from one state to anoth- er should be done in a sequence that prevents un- wanted side effects. recommended safe transi- tions are illustrated in figure 24 other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 24. interrupt i/o port state transitions the i/o port register configurations are summa- rized as follows. 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or
st72141k 35/132 i/o ports (contd) interrupt ports pa7:0, pb5:3 (with pull-up) true open drain interrupt ports pb2:0 (without pull-up) table 7. port configuration mode ddr or floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 floating interrupt input 0 1 true open drain (high sink ports) 1 x port pin name input output or = 0 or = 1 or = 0 or = 1 port a pa7:0 floating pull-up interrupt open drain push-pull port b pb5:3 floating pull-up interrupt open drain push-pull pb2:0 floating floating interrupt true open drain
st72141k 36/132 i/o ports (contd) 6.3.1 register description data register (dr) port x data register pxdr with x = a or b. read/write reset value: 0000 0000 (00h) bit 7:0 = d[7:0] data register 8 bits. the dr register has a specific behaviour accord- ing to the selected input/output configuration. writ- ing the dr register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. reading the dr register returns either the dr register latch content (pin configured as output) or the digital value applied to the i/o pin (pin configured as input). data direction register (ddr) port x data direction register pxddr with x = a or b. read/write reset value: 0000 0000 (00h) bit 7:0 = dd[7:0] data direction register 8 bits. the ddr register gives the input/output direction configuration of the pins. each bits is set and cleared by software. 0: input mode 1: output mode option register (or) port x option register pxor with x = a or b. read/write reset value: 0000 0000 (00h) bit 7:0 = o[7:0] option register 8 bits. for specific i/o pins, this register is not implement- ed. in this case the ddr register is enough to se- lect the i/o pin configuration. the or register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. each bit is set and cleared by software. input mode: 0: floating input 1: pull-up input with or without interrupt output mode: 0: output open drain (with p-buffer unactivated) 1: output push-pull (when available) 70 d7 d6 d5 d4 d3 d2 d1 d0 70 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 70 o7 o6 o5 o4 o3 o2 o1 o0
st72141k 37/132 i/o ports (contd) table 8. i/o port register map and reset values address (hex.) register label 76543210 reset value of all io port registers 00000000 0000h padr msb lsb 0001h paddr 0002h paor 0004h pbdr msb lsb 0005h pbddr 0006h pbor
st72141k 38/132 7 miscellaneous register the miscellaneous register allows control over several different features such as the external in- terrupts or the i/o alternate functions. 7.1 i/o port interrupt sensitivity description the external interrupt sensitivity is controlled by the isxx bits of the miscellaneous register. this control allows to have two fully independent exter- nal interrupt source sensitivities as shown in fig- ure 25 . each external interrupt source can be generated on four different events on the pin: n falling edge n rising edge n falling and rising edge n falling edge and low level to guaranty correct functionality, a modification of the sensitivity in the miscr register must be done only when the i bit of the cc register is set to 1 (in- terrupt masked). see i/o port register and miscel- laneous register descriptions for more details on the programming. figure 25. external interrupt sensitivity 7.2 i/o port alternate functions the miscr register manages the spi ss pin al- ternate function configuration. this makes it possi- ble to use the pb2 i/o port function while the spi is active. these functions are described in detail in section 7.4 miscellaneous register description . 7.3 clock prescaler selection the miscr register is used to select the slow mode (see section 5.4 slow mode for more de- tails) and the spi and motor control peripheral clock prescaler. ei0 interrupt source is00 is01 miscr sensitivity control pa7 pa0 pb7 pb0 is10 is11 miscr sensitivity control ei1 interrupt source
st72141k 39/132 miscellaneous register (contd) 7.4 miscellaneous register description miscellaneous register (miscr) read/write reset value: 0000 0000 (00h) bit 7 = xt16 mtc and spi clock selection this bit is set and cleared by software. the maxi- mum allowed frequency is 4mhz. 0: mtc and spi clock supplied with f osc /2 1: mtc and spi clock supplied with f osc /4 bit 6 = ssm ss mode selection this bit is set and cleared by software. 0: normal mode - the level of the spi ss signal is the external ss pin. 1: i/o mode, the level of the spi ss signal is read from the ssi bit. bit 5 = ssi ss internal mode this bit replaces the ss pin of the spi when the ssm bit is set to 1. (see spi description). it is set and cleared by software. bits 4:3 = is1[1:0] ei1 sensitivity the interrupt sensitivity defined using the is1[1:0] bits combination is applied to the ei1 external in- terrupts. these two bits can be written only when the i bit of the cc register is set to 1 (interrupt masked). ei1: port b bits 2:1 = is0[1:0] ei0 sensitivity the interrupt sensitivity defined using the is0[1:0] bits combination is applied to the ei1 external in- terrupts. these two bits can be written only when the i bit of the cc register is set to 1 (interrupt masked). ei0: port a bit 0 = sms slow mode select this bit is set and cleared by software. 0: normal mode. f cpu = f osc / 2 1: slow mode. f cpu = f osc / 32 see sections on low power consumption mode and mcc for more details. table 9. miscellaneous register map and reset values 70 xt16 ssm ssi is11 is10 is01 is00 sms is11 is10 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge is01 is00 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge address (hex.) register label 76543210 0020h miscr reset value xt16 0 ssm 0 ssi 0 is11 0 is10 0 is01 0 is00 0 sms 0
st72141k 40/132 8 on-chip peripherals 8.1 motor controller (mtc) 8.1.1 introduction the st7 motor controller (mtc) can be seen as a pulse width modulator multiplexed on six output channels, and a back electromotive force (bemf) zero-crossing detector for sensorless con- trol of permanent magnet direct current (pmdc) brushless motors. the mtc is particularly suited to driving synchro- nous motors and supports operating modes like: C commutation step control with motor voltage regulation and current limitation C commutation step control with motor current regulation, i.e. direct torque control C sensor or sensorless motor phase commutation control C bemf zero-crossing detection with high sensitiv- ity. the integrated phase voltage comparator is directly referred to the full bemf voltage without any attenuation. a bemf voltage down to 200 mv can be detected, providing high noise immunity and self-commutated operation in a large speed range. C realtime motor winding demagnetization detec- tion for fine-tuning the phase voltage masking time to be applied before bemf monitoring. C automatic and programmable delay between bemf zero-crossing detection and motor phase commutation. 8.1.2 main features n two on-chip analog comparators, one for bemf zero-crossing detection with 100 mv hysteresis, the other for current regulation or limitation n four selectable reference voltages for the hysteresis comparator (0.2 v, 0.6 v, 1.2 v, 2.5 v) n 8-bit timer (mtim) with two compare registers and two capture features n measurement window generator for bemf zero-crossing detection n auto-calibrated prescaler with 16 division steps n 8x8-bit multiplier n phase input multiplexer n sophisticated output management: C the six output channels can be split into two groups (odd & even). C the pwm signal can be multiplexed on even, odd or both groups, alternatively or simultane- ously. C the output polarity is programmable channel by channel. C an software enabled bit (active low) forces the outputs in hiz. C an emergency stop input pin (active low) asynchronously forces the outputs in hiz. table 10. mtc registers 8.1.3 application example this example shows a six-step command se- quence for a 3-phase permanent magnet dc brushless motor (pmdc motor). figure 27 shows the phase steps and voltage, while table 11 shows the relevant phase configurations. to run this kind of motor efficiently, an autoswitch- ing mode has to be used, i.e. the position of the ro- tor must self-generate the powered winding com- mutation. the bemf zero crossing (z event) on the non-excited winding is used by the mtc as a rotor position sensor. the delay between this event and the commutation is computed by the mtc and the commutation event c n is automati- cally generated after this delay. after the commutation occurs, the mtc waits until the winding is completely demagnetized by the free-wheeling diode: during this phase the winding is tied to 0v or to the hv high voltage rail and no bemf can be read. at the end of this phase a new bemf zero-crossing detection is enabled. the end of demagnetization event (d), is also de- tected by the mtc or simulated with a timer com- pare feature when no detection is possible. register description page mtim timer counter register 67 mzprv capture z n-1 register 67 mzreg capture z n register 67 mcomp compare c n+1 register 67 mdreg demagnetization register 67 mwght a n weight register 67 mprsr prescaler & sampling register 67 mimr interrupt mask register 68 misr interrupt status register 68 mcra control register a 69 mcrb control register b 70 mphst phase state register 71 mpar parity register 71 mpol polarity register 71
st72141k 41/132 motor controller (contd) the mtc manages these three events always in the same order: z generates c after a delay com- puted in realtime, then waits for d in order to ena- ble the peripheral to detect another z event. the speed regulation is managed by the micro- controller, by means of an adjustable reference current level in case of current control, or by direct pwm duty-cycle adjustment in case of voltage control. all detections of z n events are done during a short measurement window while the high side switch is turned off. for this reason the pwm signal is ap- plied on the high side switches. when the high side switch is off, the high side winding is tied to 0v by the free-wheeling diode, the low side winding voltage is also held at 0v by the low side on switch and the complete bemf voltage is present on the third winding: detection is then possible. figure 26. chronogram of events (in autoswitched mode) c event z event cn processing wait for c n t z n c n t z > z n min c > c n min wait for d n d h event d n d s event wait for z v dd v ss p signal when sampled (output of the v ref (threshold value for voltage on phase a voltage on phase b voltage on phase c analog mux) input comparator) bemf sampling
st72141k 42/132 motor controller (contd) figure 27. example of command sequence for 6-step mode (typical 3-phase pmdc motor control) 0 1 2 3 4 5 a b c node step s 1 s 2 s 3 s 4 s 5 s 6 s 1 s 2 s 3 c a b hv t4 t1 t0 t3 t2 t5 i 4 i 1 i 3 i 6 i 2 i 5 hv hv/2 0 hv hv/2 0 hv hv/2 0 demagnetization d 2 z 2 c 2 c 4 d 5 z 5 s 2 s 3 s 4 s 5 commutation delay wait for bemf = 0 hv hv/2 0v t note: control & sampling pwm influence is not represented on these simplified chronograms. switch s 1 s 6 pwm off pulses (bemf induced by rotor) superimposed voltage - approx. hv/2 (pwm on) - approx. 0v (pwm off)
st72141k 43/132 motor controller (contd) table 11. step configuration summary for a detailed description of the mtc registers, see section 8.1.7. configuration step s 1 s 2 s 3 s 4 s 5 s 6 phase state register current direction a to b a to c b to c b to a c to a c to b high side t0 t0 t2 t2 t4 t4 low side t5 t1 t1 t3 t3 t5 oo[5:0] bits in mphst register 100001 000011 000110 001100 011000 110000 bemf input measurement done on: mcic mcib mcia mcic mcib mcia is[1:0] bits in mphst register 10 01 00 10 01 00 bemf edge back emf shape falling rising falling rising falling rising cpb bit in mcrb register (zvd bit = 0) 010101 hardware or hardware-software demagnetization voltage on measured point at the start of demagnetization 0v hv 0v hv 0v hv hdm-sdm bits in mcrb register 10 11 10 11 10 11 demagnetization switch pwm side selection to accelerate demagnetization odd side even side odd side even side odd side even side driver selection to accelerate de- magnetization t5 t0 t1 t2 t3 t4
st72141k 44/132 motor controller (contd) 8.1.4 functional description the mtc can be split into four main parts as shown in the simplified block diagram in figure 28 . C the bemf zero-crossing detector with a comparator and an input multiplexer. C the delay manager with an 8-bit timer (mtim) and an 8x8 bit multiplier. C the pwm manager, including a measurement window generator, a mode selector and a current comparator. C the channel manager with the pwm multi- plexer, polarity programming capability and emergency hiz configuration input. 8.1.4.1 input detection block this block can operate in sensor mode or sensor- less mode. the mode is selected via the sr bit in the mcra register. the block diagram is shown in figure 29 . figure 28. simplified mtc block diagram mcia mcib mcic bemf=0 mco5 mco4 mco3 mco2 mco1 mco0 phase timer delay = weight x zn mccfi ocp1a nmces delay =? capture zn commute [c] measurement window generator current voltage mode internal v ref weight pwm ( 1 ) note 1: the pwm signal is generated by the st7 16-bit timer (i) (v) (v) (i) (v) r 1ext c ext (i) delay manager channel manager bemf zero-crossing detector pwm manager [z] (v) (i) [z] : back emf zero-crossing event z n : time elapsed between two consecutive z events [c] : commutation event c n : time delayed after z event to generate c event (i): current mode (v): voltage mode mtim r 2ext v dd
st72141k 45/132 motor controller (contd) input pins the mcia, mcib and mcic input pins can be used as analog pins in sensorless mode or as dig- ital pins in sensor mode. in sensorless mode, the analog inputs are used to measure the bemf zero crossing and to detect the end of demagnetization if required. in sensor mode, they are connected to sensor outputs. due to the presence of diodes, these pins can per- manently support an input current of 5 ma. in sen- sorless mode, this feature enables the inputs to be connected to each motor phase through a single resistor. note : in high voltage applications, in sensorless mode and for certain motors and power topologies (with parasitic capacitance or other), it may be re- quired to add external pull-up schottky 0.4 v (e.g. bat48) diodes on the mcia, mcib and mcic pins. a multiplexer, programmed by the is[1:0] bits in mphst register selects the input pins and con- nects them to the rotor position control logic in ei- ther sensorless or sensor mode. figure 29. input stage v ref input n sel reg vr[1:0] mcic mcia mcib a b c is[1:0] c p 00 01 10 + - external input block input comparator block event detection dq cp zvd bit hdm n bit* z d h sr bit or or or or 1 2 1 2 20 m s / d 20 m s / c cpb n bit* reo bit c d s,h cpb n bit* v i 16-bit timer pwm sampling frequency v0c1 bit freq (t=1.25 m s) for demagnetization and sensors sample sample c d s,h * = preload register, mphst register mpar register mcra register mcrb register mpar register mcrb register mcra register mcrb register reg c d s,h z events: commutation befm z ero-crossing end of d emagnetization e emergency stop notes: updated/shifted on r ratio updated (+1 or -1) multiplier o verflow r +/- o c urrent mode v oltage mode i v reg n updated with reg n+1 on c 1 2 branch taken after c event branch taken after d event changes taken into account at next c event.
st72141k 46/132 motor controller (contd) sensorless mode this mode is used to detect bemf zero crossing and end of demagnetization events. the analog phase multiplexer connects the non- excited motor winding to an analog 100mv hyster- esis comparator referred to a selectable reference voltage. the vr[1:0] bits in the mcrb register select the reference voltage from four internal values de- pending on the noise level and the application volt- age supply. bemf detections are performed during the meas- urement window, when the excited windings are free-wheeling through the low side switches and diodes. at this stage the common star connection voltage is near to ground voltage (instead of v dd /2 when the excited windings are powered) and the complete bemf voltage is present on the non-ex- cited winding terminal, referred to the ground ter- minal. the zero crossing sampling frequency is then de- fined, in current mode, by the measurement win- dow generator frequency (sa[3:0] bits in the mprsr register) or, in voltage mode, by the 16-bit timer pwm frequency and duty cycle. during a short period after a phase commutation (c event), the winding is no longer excited but needs a demagnetisation phase during which the bemf cannot be read. a demagnetization current goes through the free-wheeling diodes and the winding voltage is stuck at the high voltage or to the ground terminal. for this reason an end of de- magnetization event d must be detected on the winding before the detector can sense a bemf zero crossing. for the end-of-demagnetization detection, no spe- cial pwm configuration is needed, the comparator sensing is done at a fixed 800khz sampling fre- quency. so, the three events: c (commutation), d (demag- netization) and z (bemf zero crossing) must al- ways occur in this order. the comparator output is processed by a detector that automatically recognizes the d or z event, de- pending on the cpb or zvd edge and level config- uration bits as described in table 12 . a 20 - s filter after a c event disables a d event if spurious spikes occur. another 20 - s filter after a d event disables a z event if spurious spikes occur. table 12. zvd and cpb edge selection bits zvd bit cpb bit event generation vs input data sampled 00 01 10 11 note: the zvd bit is located in the mpar register, the cpb bit is in the mcrb register. cd h z 20-s filter 20-s filter cd h z 20-s filter 20-s filter cd h z 20-s filter 20-s filter cd h z 20-s filter 20-s filter
st72141k 47/132 motor controller (contd) demagnetization (d) event at the end of the demagnetization phase, current no longer goes through the free-wheeling diodes. the voltage on the non-excited winding terminal goes from one of the power rail voltages to the common star connection voltage plus the bemf voltage. in some cases (if the bemf voltage is positive and the free-wheeling diodes are at ground for example) this end of demagnetization can be seen as a voltage edge on the selected mcix input and it is called a hardware demagneti- zation event d h . see table 12 . if enabled by the hdm bit in the mcrb register, the current value of the mtim timer is captured in register mdreg when this event occurs in order to be able to simulate the demagnetization phase for the next steps. when enabled by the sdm bit in the mcrb regis- ter, demagnetization can also be simulated by comparing the mtim timer with the mdreg regis- ter. this kind of demagnetization is called software demagnetization d s . if the hdm and sdm bits are both set, the first event that occurs, triggers a demagnetization event. for this to work correctly, a d s event must not precede a d h event because the latter could be detected as a z event. software demagnetization can also be always used if the hdm bit is reset and the sdm bit is set. this mode works as a programmable masking time between the c and z events. to drive the mo- tor securely, the masking time must be always greater than the real demagnetization time in order to avoid a spurious z event. when an event occurs, (either d h or d s ) the di bit in the misr register is set and an interrupt request is generated if the dim bit of register mimr is set. warning 1: due to the alternate automatic capture and compare of the mtim timer with mdreg reg- ister by d h and d s events, the mdreg register should be manipulated with special care. warning 2: to avoid a system stop, the value writ- ten to the mdreg register in soft demagnetiza- tion mode (sdm = 1) should always be: C greater than the mcomp value of the commuta- tion before the related demagnetization C greater than the value in the mtim counter at that moment (when writing to the mdreg regis- ter). figure 30. d event generation mechanism mtim [8-bit up counter] d s mdreg [d n ] compare 8 d h d s hdm bit d = d h & hdm bit + d s & sdm bit d h sdm bi t f(x) d register updated on r event sdm bit hdm n bit* d h or 1 2 20 s / c cpb n bit * c d s,h sample to z event detection sr bit 20 m s / c * = preload register, changes taken into account at next c event to interrupt generator mcra register mcrb register mcrb register
st72141k 48/132 motor controller (contd) table 13. demagnetisation (d) event generation (example for zvd=0) hdm bit meaning cpb bit = 1 (even s) cpb bit = 0 (odd s) 0 software mode (sdm bit =1 and hdm bit = 0) d = d s = output compare [mdreg, mtim registers] 1 hardware/simulat- ed mode (sdm bit = 1 and hdm bit = 1) d = d h + d s (hardware detection or output compare true) d = d h (hardware detection only) (*) note: this is a zoom to the additional voltage induced by the rotor (back emf) z c s 2 hv hv/2 0v d s z c s 2 hvv hv/2 0v d s undershoot due to motor parasite or first weak / null undershoot and (*) (*) sampling bemf positive d s z s 5 hvv hv/2 0v c (*) z c s 2 hv hv/2 0v z c s 2 hv hv/2 0v d s undershoot due to motor parasite or first weak / null undershoot and (*) (*) d h d s sampling bemf positive d h z s 5 hv hv/2 0v c (*)
st72141k 49/132 motor controller (contd) bemf zero crossing (z) event when both c and d events have occurred, the pwm may be switched to another group of outputs (depending on the os[2:0] bits in the mcrb regis- ter) and the real bemf zero crossing sampling can start (see figure 32 ). a bemf voltage is present on the non-powered terminal but referred to common star connection of the motor whose voltage is equal to v dd /2. when a winding is free-wheeling (during pwm off- time) its terminal voltage changes to the other power rail voltage, that means if the pwm is ap- plied on the high side driver, free-wheeling will be done through the high side diode and the terminal will be 0v. this is used to force the common star connection to 0v in order to read the bemf referred to the ground terminal. consequently, bemf reading (i.e. comparison with a voltage close to 0v) can only be done when the pwm is applied on the high side drivers. for this reason the mtc outputs can be split in two groups called odd and even and the bemf reading will be done only when pwm is applied on one of these two groups. the reo bit in the mpar register is used to select the group to be used for bemf sensing (high side group) refer to table 15 for an overview of when a bemf can be read depending on reo bit, pwm mode and function mode of peripheral. depending on the edge and level selection (zvd and cpb) bits and when pwm is applied on the correct group, a bemf zero crossing detection sets the zi bit in the misr register and generates an interrupt if the zim bit is set. the z event also triggers some timer/multiplier op- erations, for more details see section 8.1.4.2 figure 31. sampling and zero crossing blocks output of hysteresis comparator dq cp 1 2 v i 16-bit timer pwm sampling frequency v0c1 bit freq. (t=1.25us) for demagnetization and sensor sample c d s, h 1 2 20 m s / d reo bit c d s,h sample z sr bit to d detection zvd bit or or or cpb n bit* * = preload register, changes taken into account at next c event. mcra register mpar register mcrb register mpar register mcra register reg c d s,h z events: commutation befm z ero-crossing end of d emagnetization e emergency stop notes: updated/shifted on r ratio updated (+1 or -1) multiplier o verflow r +/- o c urrent mode v oltage mode i v reg n updated with reg n+1 on c 1 2 branch taken after c event branch taken after d event
st72141k 50/132 motor controller (contd) sensor mode in sensor mode, the rotor position information is given to the peripheral by means of logical data on the three inputs mcia, mcib and mcic. for each step one of these three inputs is selected (is[1:0] bits in register mphst) in order to detect the z event. in this case demagnetization has no meaning and the relevant features such as the special pwm configuration, d s or d h management, 20-s filter; are not available (see table 14 ). for this configuration the rotor detection doesnt need a particular phase configuration to validate the measurement and a z event can be read from any detection window. a fixed sampling frequency (800 khz) is used, that means the z event and po- sition sensoring is more precise than it is in sen- sorless mode. the minimum off time for current control pwm is also reduced to 1.25 m s. procedure for reading sensor inputs in direct access mode : in direct access mode, the periph- eral clock is disabled as shown in table 25 . as the data present on the selected input is synchronized by a 800 khz clock, the sensor cant be read di- rectly (the value is latched). to read the sensor data the following steps have to be performed: 1. select the appropriate mcix input pin by means of the is[1:0] bits in the mphst register 2. switch from direct access mode to indirect access mode in order to latch the sensor data (dac bit in mcra register). 3. switch back to direct access mode. 4. read the comparator output (hst bit in the mimr register) table 14. sensor mode selection sr bit mode os2 bit use event detection sampling clock filtering behaviour of the output pwm 0 sensors not used enabled d: clock 1.25 m s z: sa&ot config. 20 m s after c for d event 20 m s after d for z event before d behaviour & after d behaviour 1 sensors used disabled z: clock 1.25 m s20 m s after c for z event only after d behaviour
st72141k 51/132 motor controller (contd) figure 32. functional diagram of z detection after d event begin end d s or d h change the side according to os[2:0] switch sampling clock[d] -> sampling clock[z] wait for next sampling clock edge yes no yes no yes no read enable by reo ? filter off ? read enabled 20 m s filter turned on side change on output pwm ?
st72141k 52/132 motor controller (contd) table 15. modes permitting bemf reading after demagnetization (d event) sr bit (sensor/ sensor- less mode) demagnet- ization v0c1 bit (voltage/ current mode) os[2:0] bits (pwm output config.) significant pwm group reo bit (read bemf on even/odd group) bemf reading permitted after d event when: 0 after d event 1 x00 even 0 sensorless mode, current mode, pwm output only on even group and bemf read on even group x01 odd 1 sensorless mode, current mode, pwm output only on odd group and bemf read on odd group x10 even 0 sensorless mode, current mode, pwm output on alternate groups but bemf read only on even group x10 odd 1 sensorless mode, current mode, pwm output on alternate groups but bemf read only on odd group 0 000 even 0 sensorless mode, voltage mode, pwm output only on even group and bemf read on even group 001 odd 1 sensorless mode, voltage mode, pwm output only on odd group and bemf read on odd group 100 even 0 sensorless mode, voltage mode, pwm output only on even group and bemf read on even group 101 odd 1 sensorless mode, voltage mode, pwm output only on odd group and bemf read on odd group 110 even 0 sensorless mode, voltage mode, pwm output on alternate groups but bemf read only on even group 110 odd 1 sensorless mode, voltage mode, pwm output on alternate groups but bemf read on odd group x x11 even and odd x sensorless mode, current or voltage mode, pwm output on both groups, bemf read on either group 1 not used x xxx odd or even x sensor mode, in any pwm output configu- ration, bemf read on either group other cases bemf reading forbidden
st72141k 53/132 motor controller (contd) 8.1.4.2 delay manager figure 33. overview of mtim timer this part of the mtc contains all the time-related functions, its architecture is based on an 8-bit shift left/shift right timer shown in figure 33 . the mtim timer includes: C an auto-updated prescaler C a capture/compare register for software demag- netization simulation (mdreg) C two cascaded capture register (mzreg and mzprv) for storing the times between two con- secutive bemf zero crossings (z events) C an 8x8 bit multiplier for auto computing the next commutation time C one compare register for phase commutation generation (mcomp) the mtim timer module can work in two main modes. in switched mode the user must process the step duration and commutation time by soft- ware, in autoswitched mode the commutation ac- tion is performed automatically depending on the rotor position information and register contents. table 16. switched and autoswitched modes switched mode this feature allows the motor to be run step-by- step. this is useful when the rotor speed is still too low to generate a bemf. it can also run other kinds of motor without bemf generation such as induction motors or switch reluctance motors. this mode can also be used for autoswitching with all computation for the next commutation time done by software (hardware multiplier not used) and us- ing the powerful interrupt set of the peripheral. in this mode, the step time is directly written by software in the commutation compare register mcomp. when the mtim timer reaches this value a commutation occurs (c event) and the mtim timer is reset. 8-bit up counter mtim mzreg [z n ] mzprv [z n-1 ] c d s mdreg [d n ] compare compare mcomp [c n+1 ] z z d h ck c d s,h z 8 t ratio sdm bit z clr 1 0 c swa bit 20 m s/c = register updated on r event to interrupt generator to interrupt generator to interrupt generator mcra register mcrb register swa bit commutation type mcomp user access 0 switched mode read/write 1 autoswitched mode read only
st72141k 54/132 motor controller (contd) at this time all registers with a preload function are loaded (registers marked with (*) in section 8.1.7). the ci bit of misr is set and if the cim bit in the misr register is set an interrupt is generated. an overflow of the mtim timer generates an rpi interrupt if the rim bit is set. the mtim timer prescaler (step ratio bits st[3:0] in the mprsr register) is user programmable. ac- cess to this register is not allowed while the mtim timer is running (access is possible only before the starting the timer by means of the moe bit) but the prescaler contents can be incremented/decre- mented at the next commutation event by setting the rmi (decrement) or rpi (increment) bits in the misr register. when this method is used, at the next commutation event the prescaler value will be updated but also all the mtim timer-related regis- ters will be shifted in the appropriate direction to keep their value. after it has been taken into ac- count, (at commutation) the rpi or rmi bit is reset. see table 17 . only one update per step is allowed, so if both rpi and rmi are set together, rpi is taken into ac- count at the next commutation and rmi is used one commutation latter. in switched mode, bemf and demagnetization de- tection are already possible in order to pass in au- toswitched mode as soon as possible but z and d events do not affect the timer contents. warning : in this mode, mcomp must never be written to 0. table 17. step ratio update moe bit swa bit clock state read ratio increment (slow down) ratio decrement (speed-up) 0 x disabled always possible write the st[3:0] value directly in the mprsr register 1 0 enabled set rpi bit in the misr register till next commutation set rmi bit in the misr register till next commutation 1 1 enabled automatically updated according to mzreg value
st72141k 55/132 motor controller (contd) figure 34. step ratio functional diagram 4mhz st[3:0] bits 4 1 / 2ratio 1 / 2 zn < 55h? mtim timer = ffh? +1 -1 ck tratio r+ r- 2 mhz - 62.5 hz ratio > 0? ratio = ratio - 1 zn = zn x 2 zn+1 = zn+1 x 2 dn = dn x 2 counter = counter x 2 begin end yes no z capture with mtim timer underflow (zn < 55h) ratio < fh? ratio = ratio + 1 zn = zn / 2 zn+1 = zn+1/2 dn = dn/2 counter = counter/2 begin end yes no mtim timer overflow mtim timer control over t ratio and register operation slow-down control speed-up control re-compute c n compute c n mprsr register
st72141k 56/132 motor controller (contd) autoswitched mode in this mode the mcomp register content is auto- matically computed in real time as described be- low and in figure 35 . this register is read only. the c event has no effect on the contents of the mtim timer. when a z event occurs the mtim timer value is captured in the mzreg register, the previous cap- tured value is shifted into the mzprv register and the mtim timer is reset. see figure 26 . one of these two registers (depending on the dcb bit in the mcra register) is multiplied with the con- tents of the mwght register and divided by 32. the result is loaded in the mcomp compare reg- ister, which automatically triggers the next com- mutation (c event) table 18. multiplier result when an overflow occurs during the multiply oper- ation, ffh is written in the mcomp register and an interrupt (o event) is generated if enabled by the oim bit in the mimr register. figure 35. commutation processor block when the timer reaches this value an rpi interrupt is generated (timer overflow). after each shift operation the multiply is recomput- ed for greater precision. using either the mzreg or mzprv register de- pends on the motor symmetry and type. the mwght register gives directly the phase shift between the motor driven voltage and the bemf. this parameter generally depends on the motor and on the speed. auto-updated step ratio register: in switched mode, the mtim timer is driven by software only and any prescaler change has to be done by soft- ware (see section 8.1.4.2 for more details). C in autoswitched mode an auto-updated prescal- er always configures the mtim timer for best ac- curacy. figure 34 shows process of updating the step ratio bits: C when the mtim timer value reaches ffh, the prescaler is automatically incremented in order to slow down the mtim timer and avoid an over- flow. to keep consistent values, the mtim regis- ter and all the relevant registers are shifted right (divided by two). the rpi bit in the misr register is set and an interrupt is generated (if rim is set). C when a z-event occurs, if the mtim timer value is below 55h, the prescaler is automatically dec- remented in order to speed up the mtim timer and keep precision better than 1.2%. the mtim register and all the relevant registers are shifted left (multiplied by two). the rmi bit in the misr register is set and an interrupt is generated if rim is set. C if the prescaler contents reach the value 0, it can no longer be automatically decremented, the mtc continues working with the same prescaler value, i.e. with a lower accuracy. no rmi in- terrrupt can be generated. C if the prescaler contents reach the value 15, it can no longer be automatically incremented. when the timer reaches the value ffh, the pres- caler and all the relevant registers remain un- changed and no interrupt is generated, the timer clock is disabled, and its contents stay at ffh the pwm is still generated and the d and z de- tection circuitry still work, enabling the capture of the maximum timer value. the automatically updated registers are: mtim, mzreg, mzprv, mcomp and mdreg. access to these registers is summarised in table 21 . dcb bit commutation delay 0 mcomp = mwght x mzprv / 32 1 mcomp = mwght x mzreg / 32 mwght [a n+1 ] mzreg [z n ] a x b / 32 mzprv [z n-1 ] 3 dcb bit swa bit mcomp [c n+1 ] z set 8 8 8 n n-1 o to = register updated on r event generator interrupt mcra register mcra register
st72141k 57/132 motor controller (contd) table 19. mtim timer-related registers note on using the auto-updated mtim timer: the auto-updated mtim timer works accurately within its operating range but some care has to be taken when processing timer-dependent data such as the step duration for regulation or demagnetiza- tion. for example if an overflow occurs when calculat- ing a software end of demagnetization (mcomp+demagnetisation_time>ffh), the value that stored in mdreg will be: 7fh+(mcomp+demagnetization_time-ffh)/2. note on commutation interrupts: it is good prac- tice to modify the configuration for the next step as soon as possible, i.e within the commutation inter- rupt routine. all registers that need to be changed at each step have a preload register that enables the modifica- tions for a complete new configuration to be per- formed at the same time (at c event in normal mode or when writing the mphst register in direct access mode). these configuration bits are: cpb, hdm, sdm and os2 in the mcrb register and is[1:0], oo[5:0] in the mphst register. note on initializing the mtc: as shown in table 21 all the mtim timer registers are in read-write mode until the mtc clock is enabled (with the moe and dac bits). this allows the timer, prescal- er and compare registers to be properly initialized for start-up. in sensorless mode, the motor has to be started in switched mode until a bemf voltage is present on the inputs. this means the prescaler st[3:0] bits and mcomp register have to be modified by soft- ware. when running the st[3:0] bits can only be incremented/decremented, so the initial value is very important. when starting directly in autoswitched mode (in sensor mode for example), write an appropriate value in the mzreg and mzprv register to per- form a step calculation as soon as the clock is en- abled. name reset value contents mtim 00h timer value mzprv 00h capture zn-1 mzreg 00h capture zn mcomp 00h compare cn+1 mdreg 00h demagnetization dn
st72141k 58/132 motor controller (contd) the figure 36 gives the step ratio register value (left axis) and the number of bemf sampling dur- ing one electrical step with the corresponding ac- curacy on the measure (right axis) as a function of the mechanical frequency. for a given prescaler value (step ratio register) the mechanical frequency can vary between two fixed values shown on the graph as the segment ends. in autoswitched mode, this register is automatical- ly incremented/decremented when the step fre- quency goes out of this segment. at f cpu =4mhz, the range covered by the step ra- tio mechanism goes from 2.39 to 235000 (pole pair x rpm) with a minimum accuracy of 1.2% on the step period. to read the number of samples for zn within one step (right y axis), select the mechanical frequen- cy on the x axis and the sampling frequency curve used for bemf detection (pwm frequency or measurment window frequency). for example, for n.frpm = 15,000 and a sampling frequency of 20khz, there are approximately 10 samples in one step and there is a 10% error rate on the measure- ment. figure 36. step ratio bits decoding and accuracy results and bemf sampling rate step ratio (decimal) n.frpm 1 2.39 4.79 7.18 9.57 14.4 19.1 28.7 38.3 57.4 76.6 115 153 230 306 460 614 920 1230 1840 2450 3680 4900 7350 9800 14700 19600 29400 39200 58800 78400 118000 157000 235000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 avg zn ~ 7fh 0.6% 100% bemf samples d zn/zn 0% 10% 50% 1 2 4 10 200 hz 20 khz avg zn ~ ffh 0.4% avg zn ~ 7fh 0.6% avg zn ~ ffh 0.4% avg zn ~ 55h 1.2% fn 3.fn fn+1 = 2.fn 3.fn+1 = 6.fn f step = 6.n.f rpm = n.f / 10 ? n.f = 10.f step n: pole pair number f step : electrical step frequency st[3:0] avg zn ~ 55h 1.2%
st72141k 59/132 motor controller (contd) table 20. step frequency/period range table 21. modes of accessing mtim timer-related registers step ratio bits st[3:0] maximum step frequency minimum step frequency minimum step period maximum step period 0000 23.5 khz 7.85 khz 42.5 m s 127.5 m s 0001 11.7 khz 3.93 khz 85 m s255 m s 0010 5.88 khz 1.96 khz 170 m s510 m s 0011 2.94 khz 980 hz 340 m s1.02ms 0100 1.47 khz 490 hz 680 m s2.04ms 0101 735 hz 245 hz 1.36 ms 4.08 ms 0110 367 hz 123 hz 2.72 ms 8.16 ms 0111 183 hz 61.3 hz 5.44 ms 16.32 ms 1000 91.9 hz 30.7 hz 10.9 ms 32.6 ms 1001 45.9 hz 15.4 hz 21.8 ms 65.2 ms 1010 22.9 hz 7.66 hz 43.6 ms 130 ms 1011 11.4 hz 3.83 hz 87 ms 261 ms 1100 5.74 hz 1.92 hz 174 ms 522 ms 1101 2.87 hz 0.958 hz 349 ms 1.04 s 1110 1.43 hz 0.479 hz 697 ms 2.08 s 1111 0.718 hz 0.240 hz 1.40 s 4.17 s state of mcra register bits access to mtim timer related registers rst bit swa bit moe bit mode read only access read / write access 0 0 0 configuration mode mtim, mzprv, mzreg, mcomp, mdreg, st[3:0] 0 0 1 switched mode mtim, mzprv, mzreg, st[3:0] mcomp, mdreg, rmi bit of misr: 0: no action 1: decrement st[3:0] rpi bit of misr: 0: no action 1: increment st[3:0] 0 1 0 emergency stop mtim, mzprv, mzreg, mcomp, mdreg, st[3:0] 0 1 1 autoswitched mode mtim, mzprv, mzreg, mcomp, st[3:0] mdreg,rmi, rpi bit of misr: set by hardware, (increment st[3:0]) cleared by software
st72141k 60/132 motor controller (contd) 8.1.4.3 pwm manager the pwm manager controls the motor via the six output channels in voltage mode or current mode depending on the v0c1 bit in the mcra register. a block diagram of this part is given in figure 37 . voltage mode in voltage mode (v0c1 bit = 0), the pwm is gen- erated by the 16-bit a timer. its duty cycle is programmed by software (refer to the chapter on the 16-bit timer) as required by the application (speed regulation for example). the current comparator is used for safety purpos- es as a current limitation. for this feature, the de- tected current must be present on the mccfi pin and the current limitation must be present on pin ocp1a. this current limitation is fixed by a voltage reference depending on the maximum current ac- ceptable for the motor. this current limitation is generated with the v dd voltage by means of an external divider but can also be adjusted with an external reference voltage ( 3.7 v). the external components are adjusted by the user depending on the application needs. in voltage mode, it is mandatory to set a current limitation. in sensorless mode the bemf zero crossing is done during the pwm off time. the pwm signal is directed to the channel manag- er that connects it to the programmed outputs (see figure 39 ). current mode in current mode, the pwm output signal is gener- ated by a combination of the output of the meas- urement window generator (see figure 38 ) and the output of the current comparator, and is direct- ed to the output channel manager as well ( figure 39 ). the current reference is provided to the compara- tor by the pwm output of the 16-bit timer (0.25% accuracy), filtered through a rc filter (external ca- pacitor on pin ocp1a and an internal voltage di- vider 30k and 70k). the detected current input must be present on the mccfi pin. to avoid spurious commutations due to parasitic noise after switching on the pwm, a 2.5-s filter can be applied on the comparator output by set- ting the cff bit in the mcrb register. the on state of the resulting pwm starts at the end of the measurement window (rising edge), and ends either at the beginning of the next meas- urement window (falling edge), or when the cur- rent level is reached. figure 37. current feedback mccfi 2.5- m s filter v cref r1 r2 16-bit timer - pwm ocp1a c ext common mode = v dd - (1,4...1,0)v v cref max = v dd - 1,3 v power down mode to phase state v0c1 bit cff bit sampling frequency + - control mcra register mcra (v) r 1ext r 2ext v dd (v) (i) (i) register legend : (i): current mode (v): voltage mode
st72141k 61/132 motor controller (contd) the measurement window frequency can be pro- grammed between 195hz and 25khz by the means of the sa[3:0] bits in the mprsr register. in sensorless mode this measurement window can be used to detect either end of demagnetization or bemf zero crossing events. its width can be defined between 5 m s and 30 m s in sensorless mode by the ot[1:0] bits in the mpol register. in sensor mode (sr=1) this off time is fixed at 1.25 m s. table 22. off-time table table 23. sampling frequency selection figure 38. sampling clock generation block ot1 bit ot0 bit off-time sensorless mode (sr bit=0) off-time sensor mode (sr bit =1) 00 5 m s 1.25 m s 0 1 10 m s 1 0 15 m s 1 1 30 m s sa3 sa2 sa1 sa0 sampling frequency 0000 25.0 khz 0001 20.0 khz 0010 18.1 khz 0011 15.4 khz 0100 12.5 khz 0101 10.0 khz 0110 6.25 khz 0111 3.13 khz 1000 1.56 khz 1001 1.25 khz 1010 1.14 khz 1011 961 hz 1100 781 hz 1101 625 hz 1110 390 hz 1111 195 hz frequency logic 4 mhz 1 off-time logic s q r 4 sa[3:0] bits 2 ot[1:0] bits t off t sampling ( 1 ) the mtc controller input frequency must always be 4 mhz, whatever the crystal frequency is. the appropriate internal frequency can be selected in the miscellaneous register. mprsr register mpol register
st72141k 62/132 motor controller (contd) 8.1.4.4 channel manager the channel manager consists of: C a phase state register with preload and polarity function C a multiplexer to direct the pwm to the odd and/ or even channel group C a tristate buffer asynchronously driven by an emergency input. the block diagram is shown in figure 39 . mphst phase state register a preload register enables software to asynchro- nously update (during the previous commutation interrupt routine for example) the channel configu- ration for the next step: the oo[5:0] bits in the mphst register are copied to the phase register on a c event. table 24. output state figure 39. channel manager block diagram op[5:0] bit oo[5:0] bit mco[5:0] pin 0 0 1 (off) 0 1 0-(pwm allowed) 1 0 0 (off) 1 1 1-(pwm allowed) cff bit oo bits* c oe[5:0] bits 6 6 os[2:0] bits* phase n register* sr bit 3 16-bit timer pwm sampling frequency dac bit channel [5:0] current comparator output v i 16-bit timer pwm sq r v0c1 bit v i 2.5- m s filter op[5:0] bits moe bit mco0 mco2 mco4 mco3 mco5 mco1 nmces x6 x6 6 1 mphst register mpol register mcrb register mpar register * = preload register, changes taken into account at next c event. mrca register mcra register mcra register mcra register mcra register reg c d s, h z events: commutation befm z ero-crossing end of d emagnetization e emergency stop notes: updated/shifted on r ratio updated (+1 or -1) multiplier o verflow r +/- o c urrent mode v oltage mode i v reg n updated with reg n+1 on c 1 2 branch taken after c event branch taken after d event
st72141k 63/132 motor controller (contd) direct access to the phase register is also possible when the dac bit in the mcra register is set. table 25. dac and moe bit meaning the polarity register is used to match the polarity of the power drivers keeping the same control log- ic and software. if one of the opx bits in the mpol register is set, this means the switch x is on when mcox is v dd . each output status depends also on the momen- tary state of the pwm, its group (odd or even), and the peripheral state. pwm features the outputs can be split in two pwm groups in or- der to differentiate the high side and the low side switches. this output property can be pro- grammed using the oe[5:0] bits in the mpar reg- ister table 26. meaning of the oe[5:0] bits the multiplexer directs the pwm to the upper channel, the lower channel or both of them alter- natively or simultaneously according to the periph- eral state. this means that the pwm can affect any of the up- per or lower channels allowing the selection of the most appropriate reference potential when free- wheeling the motor in order to: C improve system efficiency C speed up the demagnetization phase C enable back emf zero crossing detection. the os[2:0] bits in the mcrb register allow the pwm configuration to be configured for each case as shown in figure 41 , figure 42 and figure 40 . this configuration depends also on the current/ voltage mode (v0c1 bit in the mcra register) be- cause the os[2:0] have not the same meaning in voltage mode and in current mode. during demagnetization, the os2 bit is used to control pwm mode, and it is latched in a preload register so it can be modified when a commutation event occurs. the os[1:0] bits are used to control the pwm be- tween the d and c events. warning : in voltage mode the os[2:0] bits have a special configuration value: os[2:0] = 010. in this mode, there is no current limitation and no pwm applied to active outputs. the active outputs are always at 100% whether in demagnetization, or normal mode. note about demagnetization speed-up: during demagnetization the voltage on the winding has to be as high as possible in order to reduce the de- magnetization time. software can apply a different pwm configuration on the outputs between the c and d events, to force the free wheeling on the ap- propriate diodes to maximize the demagnetization voltage. emergency feature when the nmces pin goes low C the tristate output buffer is put in hiz asynchro- nously C the moe bit in the mcra register is reset C an interrupt request is sent to the cpu if the eim bit in the mimr register is set this bit can be connected to an alarm signal from the drivers, thermal sensor or any other security component. this feature functions even if the mcu oscillator is off. moe bit dac bit effect on output effect on mtim timer 0 x high z clock disabled 10 standard run- ning mode standard run- ning mode 11 mphst value same as mpol value clock disabled oe[5:0] channel group 0 even channel 1 odd channel
st72141k 64/132 motor controller (contd) figure 40. step behaviour of one output channel mco[n] in voltage mode (voltage mode without polarity effect) os2 pwm behaviour before d 0 1 not alternate alternate os[1:0] pwm behaviour after d 00 01 on even channels on odd channels 10 11 alternate odd/even on all active channels ! voltage (v0c1=0) off (0) x 1 0 on (1) c d c mo d e o o [ 5 : 0 ] demagnetization e v e n t o s [ 2 : 0 ] 000 odd 001 even odd 010 011 even odd even odd 100 101 110 111 even odd even odd even odd even odd even odd o e [ 1 : 0 ] even 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x step xxx os1 os0 os2 warning: os[2:0] = 010 has no current regulation!
st72141k 65/132 motor controller (contd) figure 41. step behaviour of one output channel mco[n] in current / sensorless mode figure 42. step behaviour of one output channel mco[n] in current / sensor mode c d c mo d e current (v0c1=1) o e [ 1 : 0 ] o o [ 5 : 0 ] x even (0) (current mode without polarity effect, sensorless mode: sr=0) demagnetization step e v e n t off (0) on (1) odd (1) 1 0 t off t off xx x 11 10 01 1 0 11 10 00 00 01 x xx os1 os0 os2 os2 pwm behaviour before d 0 1 on even channels on odd channels os[1:0] pwm behaviour after d 00 01 on even channels on odd channels 10 11 alternate odd/even on all active channels 1 0 1 0 1 0 1 0 1 0 c c m o d e current (v0c1=1) o e [ 5 : 0 ] o o [ 5 : 0 ] x even (0) (current mode without polarity effect, sensor mode: sr=1) step e v e n t off (0) on (1) odd (1) xx 11 10 01 11 10 00 00 01 xx os1 os0 1 0 os2 not used - os[1:0] pwm behaviour after d 00 01 on even channels on odd channels 10 11 alternate odd/even on all active channels 1.25us 1.25us in sensor mode, there is no demagnetisation event and the pwm behaviour is the same for the complete step time.
st72141k 66/132 motor controller (contd) 8.1.5 low power modes before executing a halt or wfi instruction, soft- ware must stop the motor, and may choose to put the outputs in high impedance. 8.1.6 interrupts the mtc interrupt events are connected to the three interrupt vectors (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the i-bit in the cc register is reset (rim instruction). mode description wait no effect on mtc interface. mtc interrupts exit from wait mode. halt mtc registers are frozen. in halt mode, the mtc interface is in- active. the mtc interface becomes operational again when the mcu is woken up by an interrupt with exit from halt mode capability. interrupt event event flag enable control bit exit from wait exit from halt ratio increment rpi rim yes no ratio decrement rmi yes no multiplier overflow oi oim yes no emergency stop ei eim yes no bemf zero-crossing zi zim yes no end of demagnetization di dim yes no commutation ci cim yes no
st72141k 67/132 motor controller (contd) 8.1.7 register description timer counter register (mtim) read/write reset value: 0000 0000 (00h) bits 7:0 = t[7:0] : mtim counter value. these bits contain the current value of the 8-bit up counter. capture z n-1 register (mzprv) read/write reset value: 0000 0000 (00h) bits 7:0 = zp[7:0] : previous z value. these bits contain the previous captured bemf value (z n-1 ). capture z n register (mzreg) read/write reset value: 0000 0000 (00h) bits 7:0 = zc[7:0] : current z value. these bits contain the current captured bemf val- ue (z n ). compare c n+1 register (mcomp) read/write reset value: 0000 0000 (00h) bits 7:0 = dc[7:0] : next compare value. these bits contain the compare value for the next commutation (c n+1 ). demagnetization register (mdreg) read/write reset value: 0000 0000 (00h) bits 7:0 = dn[7:0] : d value. these bits contain the compare value for software demagnetization (d n ) and the captured value for hardware demagnetization (d h ). a n weight register (mwght) read/write reset value: 0000 0000 (00h) bits 7:0 = an[7:0] : a weight value. these bits contain the a n weight value for the mul- tiplier. in autoswitched mode the mcomp register is automatically loaded with: when a z event occurs. (*) depending on the dcb bit in the mcra regis- ter. prescaler & sampling register (mprsr) read/write reset value: 0000 0000 (00h) bits 7:4 = sa[3:0] : sampling ratio. these bits contain the sampling ratio value for cur- rent mode. refer to table 23 . bits 3:0 = st[3:0] : step ratio. these bits contain the step ratio value. it acts as a prescaler for the mtim timer and is auto incre- mented/decremented with each r+ or r- event. refer to table 20 . 70 t7 t6 t5 t4 t3 t2 t1 t0 70 zp7zp6zp5zp4zp3zp2zp1zp0 70 zc7 zc6 zc5 zc4 zc3 zc2 zc1 zc0 70 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 70 dn7 dn6 dn5 dn4 dn3 dn2 dn1 dn0 70 an7an6an5an4an3an2an1an0 70 sa3 sa2 sa1 sa0 st3 st2 st1 st0 z n x mwght 32(d) or z n -1 x mwght 32(d) (*)
st72141k 68/132 motor controller (contd) interrupt mask register (mimr) read/write (except bits 7:6) reset value: 0000 0000 (00h) bit 7 = hst : hysteresis comparator value. this read only bit contains the hysteresis compa- rator output. 0: demagnetisation/bemf comparator is under v ref 1: demagnetisation/bemf comparator is above v ref bit 6 = cl : current loop comparator value. this read only bit contains the current loop compa- rator output value. 0: current detect voltage is under v cref 1: current detect voltage is above v cref bit 5 = rim : ratio update interrupt mask bit. 0: ratio update interrupts (r+ and r-) disabled 1: ratio update interrupts (r+ and r-) enabled bit 4 = oim : multiplier overflow interrupt mask bit. 0: multiplier overflow interrupt disabled 1: multiplier overflow interrupt enabled bit 3 = eim : emergency stop interrupt mask bit. 0: emergency stop interrupt disabled 1: emergency stop interrupt enabled bit 2 = zim : back emf zero-crossing interrupt mask bit. 0: bemf zero-crossing interrupt disabled 1: bemf zero-crossing interrupt enabled bit 1 = dim : end of demagnetization interrupt mask bit. 0: end of demagnetization interrupt disabled 1: end of demagnetization interrupt enabled if the hdm or sdm bit in the mcrb register is set bit 0 = cim : commutation interrupt mask bit 0: commutation interrupt disabled 1: commutation interrupt enabled interrupt status register (misr) read/write reset value: 0000 0000 (00h) bit 7 = reserved. forced by hardware to 0. bit 6 = rpi : ratio increment interrupt flag. autoswitched mode (swa bit =0) : 0: no r+ interrupt pending 1: r+ interrupt pending switched mode (swa bit =1) : 0: no r+ action 1: the hardware will increment the st[3:0] bits when the next commutation occurs and shift all timer registers right. bit 5 = rmi : ratio decrement interrupt flag. autoswitched mode (swa bit =0) : 0: no r- interrupt pending 1: r- interrupt pending switched mode (swa bit =1) : 0: no r- action 1: the hardware will decrement the st[3:0] bits when the next commutation occurs and shift all timer registers left. bit 4 = oi : multiplier overflow interrupt flag. 0: no multiplier overflow interrupt pending 1: multiplier overflow interrupt pending bit 3 = ei : emergency stop interrupt flag. 0: no emergency stop interrupt pending 1: emergency stop interrupt pending bit 2 = zi : bemf zero-crossing interrupt flag. 0: no bemf zero-crossing interrupt pending 1: bemf zero-crossing interrupt pending bit 1 = di : end of demagnetization interrupt flag. 0: no end of demagnetization interrupt pending 1: end of demagnetization interrupt pending bit 0 = ci : commutation interrupt flag 0: no commutation interrupt pending 1: commutation interrupt pending 70 hst cl rim oim eim zim dim cim 70 0rpirmioi ei zi dici
st72141k 69/132 motor controller (contd) table 27. step ratio update control register a (mcra) read/write reset value: 0000 0000 (00h) bit 7 = moe: output enable bit. 0: outputs and clocks disabled 1: outputs and clocks enabled bit 6 = rst : reset mtc registers. software can set this bit to reset all mtc registers without resetting the st7. 0: no mtc register reset 1: reset all mtc registers bit 5 = sr : sensor on/off. 0: sensorless mode 1: sensor mode table 28. sensor mode selection bit 4 = dac : direct access to phase state register. 0: no direct access (reset value). in this mode all the registers with a preload register are taken into account at the c event. 1: direct access enabled. in this mode, write a val- ue in the mphst register to access the outputs directly. all other registers with a preload regis- ter are taken into account at the same time. table 29. dac bit meaning note 1: when the mtc clock is disabled, the mtim counter is not reset but as in this case it is in write access, a reset can be done by software. note 2: in direct access mode, only logical levels (0 or 1) can be output on the mcox pins. there is no pwm signal generation in this mode. bit 3 = v0c1 : voltage/current mode 0: voltage mode 1: current mode bit 2 = swa : switched/autoswitched mode 0: switched mode 1: autoswitched mode table 30. switched and autoswitched modes bit 1 = cff : current feedback filter 0: current feedback filter disabled 1: current feedback filter enabled bit 0 = dcb : data capture bit 0: use mzprv (z n -1) for multiplication 1: use mzreg (z n ) for multiplication moe bit swa bit clock state read ratio increment (slow down) ratio decrement (speed-up) 0x disa- bled al- ways possi- ble write the st[3:0] value di- rectly in the mprsr register 10 ena- bled set rpi bit in the misr reg- ister till next commutation set rmi bit in the misr reg- ister till next commutation 11 ena- bled updated automatically ac- cording to mzreg value 70 moe rst sr dac v0c1 swa cff dcb moe bit mco[5:0] output pin state 0 tristate 1 output enabled sr bit mode os2 bit enable behaviour of the output pwm 0 sensors not used os2 enabled before d behaviour & af- ter d behaviour 1 sensors used os2 disabled only after d behaviour moe bit dac bit effect on output effect on mtim timer 0 x high z clock disabled 10 standard running mode standard running mode 11 mphst register value (depending on mpol register value) clock disabled swa bit commutation type mcomp register access 0 switched mode read/write 1 autoswitched mode read only
st72141k 70/132 motor controller (contd) table 31. multiplier result control register b (mcrb) read/write reset value: 0000 0000 (00h) bits 7:6 = vr[1:0] : bemf/demagnetization refer- ence threshold these bits select the v ref value as shown in the following table. bit 5 = cpb* : compare bit for zero-crossing de- tection. 0: zero crossing detection on falling edge 1: zero crossing detection on rising edge bit 4 = hdm* : hardware demagnetization event mask bit 0: hardware demagnetization disabled 1: hardware demagnetization enabled bit 3 = sdm* : software demagnetization event mask bit 0: software demagnetization disabled 1: software demagnetization enabled bits 2:0 = os2*,os[1:0] : operating output mode selection bits refer to the step behaviour diagrams ( figure 40 , figure 41 , figure 42 ) and table 32 . these bits are used to configure the various pwm output configurations. note : the os2 bit is the only one with a preload register. table 32. step behaviour summary note: for more details, see step behaviour dia- grams ( figure 40 , figure 41 , and figure 42 ). * preload bits, new value taken into account at next c event. dcb bit commutation delay 0 mcomp = mwght x mzprv / 32 1 mcomp = mwght x mzreg / 32 70 vr1 vr0 cpb* hdm* sdm* os2* os1 os0 vr1 vr0 v ref voltage threshold 0 0 0.2v 0 1 0.6v 1 0 1.2v 1 1 2.5v mode os2 bit pwm after c and before d os [1:0] bits pwm after d and before c voltage mode(v0c1=0) sensorless (sr=0) 0 same as after d and before c 00 on even channels 01 on odd channels 10 continuous 11 all active channels 1 alternate 00 on even channels 01 on odd channels 10 alternate odd/even 11 all active channels sensor (sr=1) x unused 00 on even channels 01 on odd channels 10 alternate odd/even 11 all active channels current mode (v0c1=1) sensorless (sr=0) 0 on even channels 00 on even channels 01 on odd channels 10 alternate odd/even 11 all active channels 1 on odd channels 00 on even channels 01 on odd channels 10 alternate odd/even 11 all active channels sensor (sr=1) x unused 00 on even channels 01 on odd channels 10 alternate odd/even 11 all active channels
st72141k 71/132 motor controller (contd) phase state register (mphst) read/write reset value: 0000 0000 (00h) bits 7:6 = is[1:0]* : input selection bits these bits select the input to connect to compara- tor as shown in the following table: table 33. input channel selection bits 5:0 = oo[5:0] *: channel on/off bits these bits are used to switch channels on/off at the next c event if the dac bit =0 or directly if dac=1 0: channel off, the relevant switch is off, no pwm possible 1: channel on the relevant switch is on, pwm is possible. table 34. oo[5:0] bit meaning * preload bits, new value taken into account at next c event. parity register (mpar) read/write reset value: 0000 0000 (00h) bit 7 = zvd : z vs d edge polarity. 0: zero-crossing and end of demagnetisation have opposite edges 1: zero-crossing and end of demagnetisation have same edge bit 6 = reo : read on even or odd channel bit 0: read the bemf signal during the off time on even channels 1: read on odd channels bits 5:0 = oe[5:0] : output parity mode. 0: output channel is even 1: output channel odd polarity register (mpol) read/write reset value: 0000 0000 (00h) bits 7:6 = ot[1:0] : off time selection. these bits are used to select the off time in sen- sorless mode as shown in the following table. table 35. off-time bit meaning bits 5:0 = op[5:0] : output channel polarity. these bits are used together with the oo [5:0] bits in the mphst register to control the output chan- nels. 0: output channel is active low 1: output channel is active high. table 36. output channel state control 70 is1* is0* oo5* oo4* oo3* oo2* oo1* oo0* is1 is0 channel selected 0 0 mcia 0 1 mcib 1 0 mcic 1 1 not used oo[5:0] output channel state 0 inactive 1 active 70 zvdreooe5oe4oe3oe2oe1oe0 70 ot1 ot0 op5 op4 op3 op2 op1 op0 ot1 ot0 off-time sensorless mode (sr=0) off-time sensor mode (sr=1) 00 5 m s 1.25 m s 0 1 10 m s 1 0 15 m s 1 1 30 m s op[5:0] bit oo[5:0] bit mco[5:0] pin 0 0 1 (off) 0 1 0 (pwm possible) 1 0 0 (off) 1 1 1 (pwm possible)
st72141k 72/132 motor controller (contd) note: the cpb, hdm, sdm, os2 bits in the mcrb and the bits oe[5:0] are marked with *. it means that these bits are taken into account at the following commutation event (in normal mode) or when a value is written in the mphst register when in direct access mode. for more details, re- fer to the description of the dac bit in the mcra register. the use of a preload register allows all the registers to be updated at the same time. warning: access to preload registers special care has to be taken with preload regis- ters, especially when using the st7 bset and bres instructions on mtc registers. for instance, while writing to the mphst register, you will write the value in the preload register. however, while reading at the same address, you will get the current value in the register and not the value of the preload register. all preload registers are loaded in the real regis- ters at the same time. in normal mode this is done automatically when a c event occurs, however in direct access mode (dac bit=1) the preload regis- ters are loaded as soon as a value is written in the mphst register.
st72141k 73/132 motor controller (contd) figure 43. detailed view of the mtc mtim [8-bit up counter] c a b hv d q cp microcontroller + v ref zvd bit - mpol reg moe bit mccfi mco0 mco2 mco4 mco3 mco5 mco1 hdm n bit is n bit board + motor cff bit vr1-0 z mci c mci a mci b d h mwght reg [a n+1 ] mzreg reg [ z n ] a x b / 32 4mhz mzprv reg [z n-1 ] 3 c d s st3-0 bits 4 dcb bi t sdm n bit swa bit mdreg reg [d n ] compare compar e mcomp reg [c n+1 ] z 1 / 2 rat i o 1 / 2 mzreg mti m z sa3-0 & 16-bit timer a used as pwm sq r v i d h nmces +1 -1 z clr x6 x6 ck mi sr reg c d s, h z e mpar reg set 6 6 8 8 8 8 1 2.5- m s / pwm reg c d s, h z events: commutation befm z ero-crossing end of d emagnetization e emergency stop notes: updated/shifted on r 1 ? 1/128 ot1-0 bits n n-1 r + r - r -/+ mimr reg o o ratio updated (+1 or -1) multiplier o verflow r +/- o 3 mphst n reg sr bit sr bit + - v cref ocp1a c ext d s, h or or or or 1 2 v i 1 2 20 m s / d 20 m s / c 1 / 32 1 / 5 c urrent mode v oltage mode i v v cref c d s,h a cpb n bit os n bits reg n updated with reg n+1 on c reo bit c d s,h < 55h? = ffh? 20 m s / c cpb n bit 1 0 swa bit c 1 2 branch taken after c event branch taken after d event (v) (i) (v) r 1ext r 2ext v dd (i) v0c1 bit mcra reg.
st72141k 74/132 motor controller (contd) table 37. mtc register map and reset values address (hex.) register name 765 4 3210 0060h mtim reset value t7 0 t6 0 t5 0 t4 0 t3 0 t2 0 t1 0 t0 0 0061h mzprv reset value zp7 0 zp6 0 zp5 0 zp4 0 zp3 0 zp2 0 zp1 0 zp0 0 0062h mzreg reset value zc7 0 zc6 0 zc5 0 zc4 0 zc3 0 zc2 0 zc1 0 zc0 0 0063h mcomp reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0064h mdreg reset value dn7 0 dn6 0 dn5 0 dn4 0 dn3 0 dn2 0 dn1 0 dn0 0 0065h mwght reset value an7 0 an6 0 an5 0 an4 0 an3 0 an2 0 an1 0 an0 0 0066h mprsr reset value sa3 0 sa2 0 sa1 0 sa0 0 st3 0 st2 0 st1 0 st0 0 0067h mimr reset value hst 0 cl 0 rim 0 oim 0 eim 0 zim 0 dim 0 cim 0 0068h misr reset value 0 rpi 0 rmi 0 oi 0 ei 0 zi 0 di 0 ci 0 0069h mcra reset value moe 0 rst 0 sr 0 dac 0 v0c1 0 swa 0 cff 0 dcb 0 006ah mcrb reset value vr1 0 vr0 0 cpb 0 hdm 0 sdm 0 os2 0 os1 0 os0 0 006bh mphst reset value is1 0 is0 0 oo5 0 oo4 0 oo3 0 oo2 0 oo1 0 oo0 006ch mpar reset value zvd 0 reo 0 oe5 0 oe4 0 oe3 0 oe2 0 oe1 0 oe0 0 006dh mpol reset value ot1 0 ot0 0 op5 0 op4 0 op3 0 op2 0 op1 0 op0 0
st72141k 75/132 8.2 watchdog timer (wdg) 8.2.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counters contents before the t6 bit be- comes cleared. 8.2.2 main features n programmable timer (64 increments of 12288 cpu cycles) n programmable reset n reset (if watchdog activated) after a halt instruction or when the t6 bit reaches zero n watchdog reset indicated by status flag figure 44. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) ? 12288 t1 t2 t3 t4 t5
st72141k 76/132 watchdog timer (contd) 8.2.3 functional description the counter value stored in the cr register (bits t6:t0), is decremented every 12288 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t6:t0) rolls over from 40h to 3fh (t6 become cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. the application program must write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. the value to be stored in the cr register must be between ffh and c0h (see table 38 . watchdog timing (fcpu = 8 mhz) ): C the wdga bit is set (watchdog enabled) C the t6 bit is set to prevent generating an imme- diate reset C the t5:t0 bits contain the number of increments which represents the time delay before the watchdog produces a reset. table 38. watchdog timing (f cpu = 8 mhz) notes: following a reset, the watchdog is disa- bled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset. 8.2.4 low power modes 8.2.5 interrupts none. 8.2.6 register description control register (cr) read/write reset value: 0111 1111 (7fh) bit 7= wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled bit 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared) if wdga=1. status register (sr) read/write reset value*: xxxx xxxx0 bit 0 = wdogf watchdog flag . this bit is set by a watchdog reset and cleared by software or a power on/off reset. this bit is useful for distinguishing power/on off or external reset and watchdog reset. 0: no watchdog reset occurred 1: watchdog reset occurred * only by software and power on/off reset cr register initial value wdg timeout period (ms) max ffh 98.304 min c0h 1.536 mode description wait no effect on watchdog. halt immediate reset generation as soon as the halt instruction is executed if the watchdog is activated (wdga bit is set). 70 wdga t6 t5 t4 t3 t2 t1 t0 70 - ------wdogf
st72141k 77/132 watchdog timer (condt) table 39. watchdog timer register map and reset values address (hex.) register label 76543210 0024h wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 0025h wdgsr reset value - 0 - 0 - 0 - 0 - 0 - 0 - 0 wdogf 0
st72141k 78/132 8.3 16-bit timer 8.3.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including measuring the pulse lengths of up to two input sig- nals ( input capture ) or generating up to two output waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the cpu clock prescaler. some st7 devices have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are synchronized after a mcu reset as long as the timer clock frequen- cies are not modified. this description covers one or two 16-bit timers. in st7 devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 8.3.2 main features n programmable prescaler: f cpu divided by 2, 4 or 8. n overflow status flag and maskable interrupt n external clock input (must be at least 4 times slower than the cpu clock speed) with the choice of active edge n output compare functions with: C 2 dedicated 16-bit registers C 2 dedicated programmable signals C 2 dedicated status flags C 1 dedicated maskable interrupt n input capture functions with: C 2 dedicated 16-bit registers C 2 dedicated active edge selection signals C 2 dedicated status flags C 1 dedicated maskable interrupt n pulse width modulation mode (pwm) n one pulse mode n 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk)* the block diagram is shown in figure 45 . *note: some timer pins may not be available (not bonded) in some st7 devices. refer to the device pin out description. when reading an input signal on a non-bonded pin, the value will always be 1. 8.3.3 functional description 8.3.3.1 counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high & low. counter register (cr): C counter high register (chr) is the most sig- nificant byte (ms byte). C counter low register (clr) is the least sig- nificant byte (ls byte). alternate counter register (acr) C alternate counter high register (achr) is the most significant byte (ms byte). C alternate counter low register (aclr) is the least significant byte (ls byte). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register (sr). (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit tim- er). the reset value of both counters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bits of the cr2 register, as illustrated in table 40 clock control bits . the value in the counter register re- peats every 131072, 262144 or 524288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency.
st72141k 79/132 16-bit timer (contd) figure 45. timer block diagram mcu-peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 0 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (status register) sr 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin pin register register note: if ic, oc and to interrupt requests have separate vectors then the last or is not present (see device interrupt vector table) (see note)
st72141k 80/132 16-bit timer (contd) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the ls byte of the count value at the time of the read. whatever the timer mode used (input capture, out- put compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: C the tof bit of the sr register is set. C a timer interrupt is generated if: C toie bit of the cr1 register is set and C i bit of the cc register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. note: the tof bit is not cleared by accessing the aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). 8.3.3.2 external clock the external clock (where available) is selected if cc0=1 and cc1=1 in the cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the exter- nal clock pin extclk that will trigger the free run- ning counter. the counter is synchronised with the falling edge of the internal cpu clock. a minimum of four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the cpu clock frequency. is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + d t other instructions beginning of the sequence sequence completed ls byte ls byte ms byte
st72141k 81/132 16-bit timer (contd) figure 46. counter timing diagram, internal clock divided by 2 figure 47. counter timing diagram, internal clock divided by 4 figure 48. counter timing diagram, internal clock divided by 8 note: the mcu is in reset state when the internal reset signal is high. when it is low, the mcu is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000
st72141k 82/132 16-bit timer (contd) 8.3.3.3 input capture in this section, the index, i , may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. the two input capture 16-bit registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition is detected by the icap i pin (see figure 5). the ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). procedure: to use the input capture function, select the fol- lowing in the cr2 register: C select the timer clock (cc[1:0]) (see table 40 clock control bits ). C select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available). and select the following in the cr1 register: C set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin C select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available). when an input capture occurs: C the icf i bit is set. C the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 50 ). C a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. other- wise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. notes: 1. after reading the ic i hr register, the transfer of input capture data is inhibited and icf i will never be set until the ic i lr register is also read. 2. the ic i r register contains the free running counter value which corresponds to the most recent input capture. 3. the 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. in one pulse mode and pwm mode only the input capture 2 function can be used. 5. the alternate inputs (icap1 & icap2) are always directly connected to the timer. so any transitions on these pins activate the input cap- ture function. moreover if one of the icap i pin is configured as an input and the second one as an output, an interrupt can be generated if the user tog- gles the output pin and if the icie bit is set. this can be avoided if the input capture func- tion i is disabled by reading the ic i hr (see note 1). 6. the tof bit can be used with an interrupt in order to measure events that exceed the timer range (ffffh). ms byte ls byte icir ic i hr ic i lr
st72141k 83/132 16-bit timer (contd) figure 49. input capture block diagram figure 50. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: a ctive edge is rising edge.
st72141k 84/132 16-bit timer (contd) 8.3.3.4 output compare in this section, the index, i , may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: C assigns pins with a programmable value if the oc i e bit is set C sets a flag in the status register C generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure: to use the output compare function, select the fol- lowing in the cr2 register: C set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. C select the timer clock (cc[1:0]) (see table 40 clock control bits ). and select the following in the cr1 register: C select the olvl i bit to applied to the ocmp i pins after the match occurs. C set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: C ocf i bit is set. C the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). C a timer interrupt is generated if the ocie bit is set in the cr1 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: d t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 de- pending on cc[1:0] bits, see table 40 clock control bits ) if the timer clock is an external clock, the formula is: where: d t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (i.e. clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: C write to the oc i hr register (further compares are inhibited). C read the sr register (first step of the clearance of the ocf i bit, which may be already set). C write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr d oc i r = d t * f cpu presc d oc i r = d t * f ext
st72141k 85/132 16-bit timer (contd) notes: 1. after a processor write cycle to the oc i hr reg- ister, the output compare function is inhibited until the oc i lr register is also written. 2. if the oc i e bit is not set, the ocmp i pin is a general i/o port and the olvl i bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3. when the timer clock is f cpu /2, ocf i and ocmp i are set while the counter value equals the oc i r register value (see figure 52 ). this behaviour is the same in opm or pwm mode. when the timer clock is f cpu /4, f cpu /8 or in external clock mode, ocf i and ocmp i are set while the counter value equals the oc i r regis- ter value plus 1 (see figure 53 ). 4. the output compare functions can be used both for generating external events on the ocmp i pins even if the input capture mode is also used. 5. the value in the 16-bit oc i r register and the olv i bit should be changed after each suc- cessful comparison in order to control an output waveform or establish a new elapsed timeout. forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. folvl i bits have no effect in either one-pulse mode or pwm mode. figure 51. output compare block diagram output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1
st72141k 86/132 16-bit timer (contd) figure 52. output compare timing diagram, f timer =f cpu /2 figure 53. output compare timing diagram, f timer =f cpu /4 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) compare register i latch 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf ocmp i pin (olvl i =1) output compare flag i (ocf i )
st72141k 87/132 16-bit timer (contd) 8.3.3.5 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure: to use one pulse mode: 1. load the oc1r register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. select the following in the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. C select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: C set the oc1e bit, the ocmp1 pin is then ded- icated to the output compare 1 function. C set the opm bit. C select the timer clock cc[1:0] (see table 40 clock control bits ). then, on a valid event on the icap1 pin, the coun- ter is initialized to fffch and the olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the value fffdh is loaded in the ic1r register. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. the oc1r register value required for a specific timing application can be calculated using the fol- lowing formula: where: t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on the cc[1:0] bits, see table 40 clock control bits ) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin (see figure 54 ). notes: 1. the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. 4. the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5. when one pulse mode is used oc1r is dedi- cated to this mode. nevertheless oc2r and ocf2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the olvl2 level is dedi- cated to one pulse mode. event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5
st72141k 88/132 16-bit timer (contd) figure 54. one pulse mode timing example figure 55. pulse width modulation mode timing example counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1 counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r=2ed0h, oc2r=34e2, olvl1=0, olvl2= 1 fffc fffd fffe 2ed0 2ed1 2ed2
st72141k 89/132 16-bit timer (contd) 8.3.3.6 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. the pulse width modulation mode uses the com- plete output compare 1 function plus the oc2r register, and so these functions cannot be used when the pwm mode is activated. procedure to use pulse width modulation mode: 1. load the oc2r register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corre- sponding to the period of the pulse if olvl1=0 and olvl2=1, using the formula in the oppo- site column. 3. select the following in the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc1r register. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc2r register. 4. select the following in the cr2 register: C set oc1e bit: the ocmp1 pin is then dedicat- ed to the output compare 1 function. C set the pwm bit. C select the timer clock (cc[1:0]) (see table 40 clock control bits ). if olvl1=1 and olvl2=0, the length of the posi- tive pulse is the difference between the oc2r and oc1r registers. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on cc[1:0] bits, see table 40 clock control bits ) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 55 ) notes: 1. after a write instruction to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. 2. the ocf1 and ocf2 bits cannot be set by hardware in pwm mode, therefore the output compare interrupt is inhibited. 3. the icf1 bit is set by hardware when the coun- ter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4. in pwm mode the icap1 pin can not be used to perform input capture because it is discon- nected from the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset after each period and icf1 can also generate an interrupt if icie is set. 5. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5
st72141k 90/132 16-bit timer (contd) 8.3.4 low power modes 8.3.5 interrupts note: the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chap- ter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 8.3.6 summary of timer modes 1) see note 4 in section 8.3.3.5 one pulse mode 2) see note 5 in section 8.3.3.5 one pulse mode 3) see note 4 in section 8.3.3.6 pulse width modulation mode mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting resumes from the previous count when the mcu is woken up by an interrupt with exit from halt mode capability or from the counter reset value when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequent- ly, when the mcu is woken up by an interrupt with exit from halt mode capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register. interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie yes no input capture 2 event icf2 yes no output compare 1 event (not available in pwm mode) ocf1 ocie yes no output compare 2 event (not available in pwm mode) ocf2 yes no timer overflow event tof toie yes no modes available resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) yes yes yes yes output compare (1 and/or 2) yes yes yes yes one pulse mode no not recommended 1) no partially 2) pwm mode no not recommended 3) no no
st72141k 91/132 16-bit timer (contd) 8.3.7 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (cr1) read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no successful comparison. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no suc- cessful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and ocxe is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1
st72141k 92/132 16-bit timer (contd) control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output com- pare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the internal output compare 1 function of the timer remains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 pin enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output com- pare mode). whatever the value of the oc2e bit, the internal output compare 2 function of the timer remains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bits 3:2 = cc[1:0] clock control. the timer clock mode depends on these bits: table 40. clock control bits note : if the external clock pin is not available, pro- gramming the external clock configuration stops the counter. bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin (extclk) will trigger the counter register. 0: a falling edge triggers the counter register. 1: a rising edge triggers the counter register. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg timer clock cc1 cc0 f cpu / 4 0 0 f cpu / 2 0 1 f cpu / 8 1 0 external clock (where available) 11
st72141k 93/132 16-bit timer (contd) status register (sr) read only reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter matches the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) register. bit 5 = tof timer overflow flag. 0: no timer overflow (reset value). 1: the free running counter has rolled over from ffffh to 0000h. to clear this bit, first read the sr register, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter matches the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) register. bit 2-0 = reserved, forced by hardware to 0. input capture 1 high register (ic1hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 icf1 ocf1 tof icf2 ocf2 0 0 0 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb
st72141k 94/132 16-bit timer (contd) output compare 2 high register (oc2hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the sr register clears the tof bit. alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to sr register does not clear the tof bit in sr register. input capture 2 high register (ic2hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb
st72141k 95/132 16-bit timer (contd) table 41. 16-bit timer register map and reset values address (hex.) register label 76543210 timer a: 32 timer b: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timer a: 31 timer b: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timer a: 33 timer b: 43 sr reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 - 0 - 0 - 0 timer a: 34 timer b: 44 ichr1 reset value msb - ------ lsb - timer a: 35 timer b: 45 iclr1 reset value msb - ------ lsb - timer a: 36 timer b: 46 ochr1 reset value msb - ------ lsb - timer a: 37 timer b: 47 oclr1 reset value msb - ------ lsb - timer a: 3e timer b: 4e ochr2 reset value msb - ------ lsb - timer a: 3f timer b: 4f oclr2 reset value msb - ------ lsb - timer a: 38 timer b: 48 chr reset value msb 1111111 lsb 1 timer a: 39 timer b: 49 clr reset value msb 1111110 lsb 0 timer a: 3a timer b: 4a achr reset value msb 1111111 lsb 1 timer a: 3b timer b: 4b aclr reset value msb 1111110 lsb 0 timer a: 3c timer b: 4c ichr2 reset value msb - ------ lsb - timer a: 3d timer b: 4d iclr2 reset value msb - ------ lsb -
st72141k 96/132 8.4 serial peripheral interface (spi) 8.4.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. the spi is normally used for communication be- tween the microcontroller and external peripherals or another microcontroller. refer to the pin description chapter for the device- specific pin-out. 8.4.2 main features n full duplex, three-wire synchronous transfers n master or slave operation n four master mode frequencies n maximum slave mode frequency = f cpu /4. n four programmable master bit rates n programmable clock polarity and phase n end of transfer interrupt flag n write collision flag protection n master mode fault protection capability. 8.4.3 general description the spi is connected to external devices through 4 alternate pins: C miso: master in slave out pin C mosi: master out slave in pin C sck: serial clock pin Css : slave select pin a basic example of interconnections between a single master and a single slave is illustrated on figure 56 . the mosi pins are connected together as are miso pins. in this way data is transferred serially between master and slave (most significant bit first). when the master device transmits data to a slave device via mosi pin, the slave device responds by sending data to the master device via the miso pin. this implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master de- vice via the sck pin). thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. a status flag is used to indicate that the i/o operation is com- plete. four possible data/clock timing relationships may be chosen (see figure 59 ) but master and slave must be programmed with the same timing mode. figure 56. serial peripheral interface master/slave 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit
st72141k 97/132 serial peripheral interface (contd) figure 57. serial peripheral interface block diagram dr read buffer 8-bit shift register write read internal bus spi spie spe spr2 mstr cpha spr0 spr1 cpol spif wcol modf serial clock generator mosi miso ss sck control state cr sr - -- -- it request master control
st72141k 98/132 serial peripheral interface (contd) 8.4.4 functional description figure 56 shows the serial peripheral interface (spi) block diagram. this interface contains 3 dedicated registers: C a control register (cr) C a status register (sr) C a data register (dr) refer to the cr, sr and dr registers in section 8.4.7 for the bit definitions. 8.4.4.1 master configuration in a master configuration, the serial clock is gener- ated on the sck pin. procedure C select the spr0 & spr1 bits to define the se- rial clock baud rate (see cr register). C select the cpol and cpha bits to define one of the four relationships between the data transfer and the serial clock (see figure 59 ). Cthe ss pin must be connected to a high level signal during the complete byte transmit se- quence. C the mstr and spe bits must be set (they re- main set only if the ss pin is connected to a high level signal). in this configuration the mosi pin is a data output and to the miso pin is a data input. transmit sequence the transmit sequence begins when a byte is writ- ten the dr register. the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: C the spif bit is set by hardware C an interrupt is generated if the spie bit is set and the i bit in the ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set 2. a read to the dr register. note: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read.
st72141k 99/132 serial peripheral interface (contd) 8.4.4.2 slave configuration in slave configuration, the serial clock is received on the sck pin from the master device. the value of the spr0 & spr1 bits is not used for the data transfer. procedure C for correct data transfer, the slave device must be in the same timing mode as the mas- ter device (cpol and cpha bits). see figure 59 . Cthe ss pin must be connected to a low level signal during the complete byte transmit se- quence. C clear the mstr bit and set the spe bit to as- sign the pins to alternate function. in this configuration the mosi pin is a data input and the miso pin is a data output. transmit sequence the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: C the spif bit is set by hardware C an interrupt is generated if spie bit is set and i bit in ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set. 2.a read to the dr register. notes: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 8.4.4.6 ). depending on the cpha bit, the ss pin has to be set to write to the dr register between each data byte transfer to avoid a write collision (see section 8.4.4.4 ).
st72141k 100/132 serial peripheral interface (contd) 8.4.4.3 data transfer format during an spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). the serial clock is used to syn- chronize the data transfer during a sequence of eight clock pulses. the ss pin allows individual selection of a slave device; the other slave devices that are not select- ed do not interfere with the spi transfer. clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits. the cpol (clock polarity) bit controls the steady state value of the clock when no data is being transferred. this bit affects both master and slave modes. the combination between the cpol and cpha (clock phase) bits selects the data capture clock edge. figure 59 , shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. the ss pin is the slave device select input and can be driven by the master device. the master device applies data to its mosi pin- clock edge before the capture clock edge. cpha bit is set the second edge on the sck pin (falling edge if the cpol bit is reset, rising edge if the cpol bit is set) is the msbit capture strobe. data is latched on the occurrence of the second clock transition. no write collision should occur even if the ss pin stays low during a transfer of several bytes (see figure 58 ). cpha bit is reset the first edge on the sck pin (falling edge if cpol bit is set, rising edge if cpol bit is reset) is the msbit capture strobe. data is latched on the oc- currence of the first clock transition. the ss pin must be toggled high and low between each byte transmitted (see figure 58 ). to protect the transmission from a write collision a low value on the ss pin of a slave device freezes the data in its dr register and does not allow it to be altered. therefore the ss pin must be high to write a new data byte in the dr without producing a write collision. figure 58. cpha / ss timing diagram mosi/miso master ss slave ss (cpha=0) slave ss (cpha=1) byte 1 byte 2 byte 3 vr02131a
st72141k 101/132 serial peripheral interface (contd) figure 59. data clock timing diagram cpol = 1) cpol = 0) miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 cpol = 1 cpol = 0 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) vr02131b msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit sclk (with sclk (with
st72141k 102/132 serial peripheral interface (contd) 8.4.4.4 write collision error a write collision occurs when the software tries to write to the dr register while a data transfer is tak- ing place with an external device. when this hap- pens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the mcu oper- ation. in slave mode when the cpha bit is set: the slave device will receive a clock (sck) edge prior to the latch of the first data transfer. this first clock edge will freeze the data in the slave device dr register and output the msbit on to the exter- nal miso pin of the slave device. the ss pin low state enables the slave device but the output of the msbit onto the miso pin does not take place until the first data transfer clock edge. when the cpha bit is reset: data is latched on the occurrence of the first clock transition. the slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the dr register after its ss pin has been pulled low. for this reason, the ss pin must be high, between each data byte transfer, to allow the cpu to write in the dr register without generating a write colli- sion. in master mode collision in the master device is defined as a write of the dr register while the internal serial clock (sck) is in the process of transfer. the ss pin signal must be always high on the master device. wcol bit the wcol bit in the sr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 60 ). figure 60. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read sr read dr write dr 2nd step spif =0 wcol=0 spif =0 wcol=0 if no transfer has started wcol=1 if a transfer has started clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 before the 2nd step read sr read dr note: writing to the dr register instead of reading in it does not reset the wcol bit read sr or then then then
st72141k 103/132 serial peripheral interface (contd) 8.4.4.5 master mode fault master mode fault occurs when the master device has its ss pin pulled low, then the modf bit is set. master mode fault affects the spi peripheral in the following ways: C the modf bit is set and an spi interrupt is generated if the spie bit is set. C the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. C the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read or write access to the sr register while the modf bit is set. 2. a write to the cr register. notes: to avoid any multiple slave conflicts in the case of a system comprising several mcus, the ss pin must be pulled high during the clearing se- quence of the modf bit. the spe and mstr bits may be restored to their original state during or af- ter this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device the modf bit can not be set, but in a multi master configuration the device can be in slave mode with this modf bit set. the modf bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a re- set or default system state using an interrupt rou- tine. 8.4.4.6 overrun condition an overrun condition occurs when the master de- vice has sent several data bytes and the slave de- vice has not cleared the spif bit issuing from the previous data byte transmitted. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the dr register returns this byte. all other bytes are lost. this condition is not detected by the spi peripher- al.
st72141k 104/132 serial peripheral interface (contd) 8.4.4.7 single master and multimaster configurations there are two types of spi systems: C single master system C multimaster system single master system a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 61 ). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written its dr regis- ter. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. multi-master system a multi-master system may also be configured by the user. transfer of master control could be im- plemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the cr register and the modf bit in the sr register. figure 61. single master configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu
st72141k 105/132 serial peripheral interface (contd) 8.4.5 low power modes 8.4.6 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi operation resumes when the mcu is woken up by an interrupt with exit from halt mode capability. interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes no master mode fault event modf yes no
st72141k 106/132 serial peripheral interface (contd) 8.4.7 register description control register (cr) read/write reset value: 0000xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever spif=1 or modf=1 in the sr register bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 8.4.4.5 master mode fault ). 0: i/o port connected to pins 1: spi alternate functions connected to pins the spe bit is cleared by reset, so the spi periph- eral is not initially connected to the external pins. bit 5 = spr2 divider enable . this bit is set and cleared by software and it is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 42 . 0: divider by 2 enabled 1: divider by 2 disabled bit 4 = mstr master. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 8.4.4.5 master mode fault ). 0: slave mode is selected 1: master mode is selected, the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are re- versed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the steady state of the serial clock. the cpol bit affects both the master and slave modes. 0: the steady state is a low value at the sck pin. 1: the steady state is a high value at the sck pin. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. bit 1:0 = spr[1 : 0] serial peripheral rate. these bits are set and cleared by software.used with the spr2 bit, they select one of six baud rates to be used as the serial clock when the device is a master. these 2 bits have no effect in slave mode. table 42. serial peripheral baud rate 70 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1
st72141k 107/132 serial peripheral interface (contd) status register (sr) read only reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag. this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the cr register. it is cleared by a soft- ware sequence (an access to the sr register fol- lowed by a read or write to the dr register). 0: data transfer is in progress or has been ap- proved by a clearing sequence. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is set, all writes to the dr register are inhibited. bit 6 = wcol write collision status. this bit is set by hardware when a write to the dr register is done during a transmit sequence. it is cleared by a software sequence (see figure 60 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = unused. bit 4 = modf mode fault flag. this bit is set by hardware when the ss pin is pulled low in master mode (see section 8.4.4.5 master mode fault ). an spi interrupt can be gen- erated if spie=1 in the cr register. this bit is cleared by a software sequence (an access to the sr register while modf=1 followed by a write to the cr register). 0: no master mode fault detected 1: a fault in master mode has been detected bits 3-0 = unused. data i/o register (dr) read/write reset value: undefined the dr register is used to transmit and receive data on the serial bus. in the master device only a write to this register will initiate transmission/re- ception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. warning: a write to the dr register places data directly into the shift register for transmission. a read to the the dr register returns the value lo- cated in the buffer and not the contents of the shift register (see figure 57 ). 70 spifwcol-modf---- 70 d7 d6 d5 d4 d3 d2 d1 d0
st72141k 108/132 serial peripheral interface (contd) table 43. spi register map and reset values address (hex.) register label 76543210 0021h spidr reset value msb xxxxxxx lsb x 0022h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0023h spisr reset value spif 0 wcol 00 modf 00000
st72141k 109/132 8.5 8-bit a/d converter (adc) 8.5.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 8 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 8 different sources. the result of the conversion is stored in a 8-bit data register. the a/d converter is controlled through a control/status register. 8.5.2 main features n 8-bit conversion n up to 8 channels with multiplexed input n linear successive approximation n data register (dr) which contains the results n conversion complete status flag n on/off bit (to reduce consumption) the block diagram is shown in figure 62 . figure 62. adc block diagram sample analog mux ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 (control status register) csr (data register) dr & hold f cpu analog to digital converter coco 0ch0 ch1 ch2 - -adon ad7 ad4 ad0 ad1 ad2 ad3 ad6 ad5
st72141k 110/132 8-bit a/d converter (adc) (contd) 8.5.3 functional description the high level reference voltage v dda must be connected externally to the v dd pin. the low level reference voltage v ssa must be connected exter- nally to the v ss pin. in some devices (refer to de- vice pin out description) high and low level refer- ence voltages are internally connected to the v dd and v ss pins. conversion accuracy may therefore be degraded by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. figure 63. recommended ext. connections characteristics: the conversion is monotonic, meaning the result never decreases if the analog input does not and never increases if the analog input does not. if input voltage is greater than or equal to v dd (voltage reference high) then results = ffh (full scale) without overflow indication. if input voltage v ss (voltage reference low) then the results = 00h. the conversion time is 64 cpu clock cycles in- cluding a sampling time of 31.5 cpu clock cycles. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. the a/d converter is linear and the digital result of the conversion is given by the formula: where reference voltage is v dd - v ss . the accuracy of the conversion is described in the electrical characteristics section. procedure: refer to the csr and dr register description sec- tion for the bit definitions. each analog input pin must be configured as input, no pull-up, no interrupt. refer to the i/o ports chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the csr register: C select the ch2 to ch0 bits to assign the ana- log channel to convert. refer to table 44 channel selection . C set the adon bit. then the a/d converter is enabled after a stabilization time (typically 30 s). it then performs a continuous conversion of the selected channel. when a conversion is complete C the coco bit is set by hardware. C no interrupt is generated. C the result is in the dr register. a write to the csr register aborts the current con- version, resets the coco bit and starts a new conversion. 8.5.4 low power modes note: the a/d converter may be disabled by re- setting the adon bit. this feature allows reduced power consumption when no conversion is need- ed. 8.5.5 interrupts none. st7 px.x/ainx v dda v ssa v dd 0.1f r ain v ain digital result = 255 x input voltage reference voltage mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilisation time before accurate conversions can be performed.
st72141k 111/132 8-bit a/d converter (adc) (contd) 8.5.6 register description control/status register (csr) read/write reset value: 0000 0000 (00h) bit 7 = coco conversion complete this bit is set by hardware. it is cleared by soft- ware reading the result in the dr register or writing to the csr register. 0: conversion is not complete. 1: conversion can be read from the dr register. bit 6 = reserved . must always be cleared. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off. 1: a/d converter is switched on. note : a typical 30 s delay time is necessary for the adc to stabilize when the adon bit is set. bit 4 = reserved . forced by hardware to 0. bit 3 = reserved . must always be cleared. bits 2:0: ch[2:0] channel selection these bits are set and cleared by software. they select the analog input to convert. table 44. channel selection * important note: the number of pins and the channel selection vary according to the device. refer to the device pinout). data register (dr) read only reset value: 0000 0000 (00h) bit 7:0 = ad[7:0] analog converted value this register contains the converted analog value in the range 00h to ffh. reading this register resets the coco flag. table 45. adc register map and reset values 70 coco - adon 0 - ch2 ch1 ch0 pin* ch2 ch1 ch0 ain0 000 ain1 001 ain2 010 ain3 011 ain4 100 ain5 101 ain6 110 ain7 111 70 ad7ad6ad5ad4ad3ad2ad1ad0 address (hex.) register label 76543210 0070h adcdr reset value is11 0 is10 0 mco 0 is21 0 is20 0 cp1 0 cp0 0 sms 0 0071h adccsr standard reset value coco 00 adon 000 ch2 0 ch1 0 ch0 0
st72141k 112/132 9 instruction set 9.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: C long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. C short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 46. st7 addressing mode overview note 1. at the time the instruction is executed, the program counter (pc) points to the instruction follow- ing jrxx. addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination/ source pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc-128/pc+127 1) + 1 relative indirect jrne [$10] pc-128/pc+127 1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3
st72141k 113/132 st7 addressing modes (contd) 9.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 9.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 9.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 9.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 9.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations
st72141k 114/132 st7 addressing modes (contd) 9.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 47. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 9.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset follows the opcode. relative (indirect) the offset is defined in memory, of which the ad- dress follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtrac- tion operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available relative direct/ indirect instructions function jrxx conditional jump callr call relative
st72141k 115/132 9.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four bytes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, di- rect bit, or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruc- tion using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf
st72141k 116/132 instruction groups (contd) mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned >
st72141k 117/132 instruction groups (contd) mnemo description function/example dst src h i n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z
st72141k 118/132 10 electrical characteristics 10.1 absolute maximum ratings this product contains devices for protecting the in- puts against damage due to high static voltages, however it is advisable to take normal precautions to avoid applying any voltage higher than the specified maximum rated voltages. for proper operation it is recommended that v i and v o be higher than v ss and lower than v dd . reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (v dd or v ss ). power considerations . the average chip-junc- tion temperature, t j , in celsius can be obtained from: t j =ta + pd x rthja where: t a = ambient temperature. rthja =package thermal resistance (junction-to ambient). p d = p int + p port . p int =i dd x v dd (chip internal power). p port =port power dissipation determined by the user) note: stresses above those listed as absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions is not implied. exposure to maximum rating condi- tions for extended periods may affect device reliability. general warning: direct connection to v dd or v ss of the reset and i/o pins could damage the device in case of unintentional internal reset generation or program counter corruption (due to unwanted change of the i/o configuration). to guarantee safe conditions, this connection has to be done through a 10k w typical pull-up or pull-down resistor. thermal characteristics symbol ratings value unit v dd - v ss supply voltage 6.5 v v in input voltage on true open drain pin v ss - 0.3 to 6.5 v input voltage on any other pin v ss - 0.3 to v dd + 0.3 v out output voltage v ss - 0.3 to v dd + 0.3 v esd esd susceptibility 2000 v i vdd_i total current into v dd_i (source) 80 ma i vss_i total current out of v ss_i (sink) 80 symbol ratings value unit r thja package thermal resistance so34 sdip32 75 60 c/w t jmax max. junction temperature 150 c t stg storage temperature range -65 to +150 c pd power dissipation 500 mw
st72141k 119/132 10.2 recommended operating conditions 10.3 dc electrical characteristics recommended operating conditions with t a =-40 to +125 o c, v dd -v ss =5v unless otherwise specified. 10.4 general timing characteristics notes: 1) unless otherwise specified, typical data is based on t a =25c and v dd -v ss =5v. this data is provided only as design guidelines and is not tested. 2) fixed frequencies required to obtain 4mhz for the motor control peripheral. 3) cpu running with memory access, all i/o pins in input mode with a static value at v dd or v ss , all peripherals switched off; clock input (osc2) driven by external square wave. 4) all i/o pins in input mode with a static value at v dd or v ss , all peripherals switched off; clock input (osc2) driven by external square wave. 5) all i/o pins in input mode with a static value at v dd or v ss . 6) data based on characterization results, not tested in production. 7) d t inst is the number of t cpu to finish the current instruction execution. general symbol parameter conditions min typ 1) max unit v dd supply voltage 4.0 5.5 v f osc resonator oscillator frequency 8 or 16 2) mhz external clock source t a ambient temperature range 1 suffix version 0 70 c 6 suffix version -40 85 3 suffix version -40 125 symbol parameter conditions min typ 1) max unit i dd supply current in run mode 3) f osc = 8 mhz, f cpu = 4 mhz f osc = 16 mhz, f cpu = 8 mhz 5 7 8 12 ma supply current in slow mode 3) f osc = 8 mhz, f cpu = 250 khz f osc = 16 mhz, f cpu = 500 khz 0.7 1 1.1 1.7 supply current in wait mode 4) f osc = 8mhz, f cpu = 4 mhz f osc = 16mhz, f cpu = 8 mhz 2 3.3 3 5 supply current in slow wait mode 4) f osc = 8 mhz, f cpu = 250 khz f osc = 16 mhz, f cpu = 500 khz 0.65 0.8 1 1.4 supply current in halt mode 5) i load = 0ma (current on ios) 200 m a v rm data retention mode 6) halt mode 2 v symbol parameter conditions min typ max unit t inst instruction time 2 12 t cpu t irt interrupt reaction time t irt = d t inst + 10 7) 10 22 t cpu
st72141k 120/132 10.5 i/o port characteristics recommended operating conditions with t a =-40 to +125 o c and 4.5v v ih v in < v il 20 50 40 120 80 240 k w i l input leakage current v ss v dd 5 ma negative 6) : v ext v dd 20 negative: v ext st72141k 121/132 10.6 supply, reset and clock characteristics 10.6.1 supply manager recommended operating conditions with t a =-40 to +125 o c and voltages referred to v ss . 10.6.2 reset sequence manager recommended operating conditions with t a =-40...+125 o c and 4.5v v ih v in 3 v ss 5 20 10 80 20 180 k w t delaymin reset delay for external and watchdog reset sources 6 30 1/f sfosc m s t pulse external reset pin pulse time 20 m s external clock source symbol parameter conditions min typ max unit v osc2h osc2 input pin high level voltage square wave signal with ~50% duty cycle 0.7xv dd v dd v v osc2l osc2 input pin low level voltage v ss 0.3xv dd crystal and ceramic resonator oscillators symbol parameter conditions min typ 5) max unit f osc oscillator frequency 6) 816mhz c li load capacitor r smax =100 w 7) 15 8) 18 21 6) pf i dd supply current 700 1100 4) m a t start oscillator start-up time depends on resonator quality. a typical value is 10ms
st72141k 122/132 10.7 memory and peripheral characteristics recommended operating conditions with t a =-40 to +125 o c and v dd -v ss =5v unless otherwise specified. note: 1) unless otherwise specified, typical data is based on t a = 25 c and v dd -v ss = 5 v. this data is provided only as de- sign guidelines and are not tested. 2) the v mtchyst hysteresis is constant. figure 64. motor control comparator characteristics eprom symbol parameter conditions min typ max unit w erase uv lamp lamp wavelength 2537? 15 w-sec/cm 2 t erase erase time uv lamp placed 1 inch from the device window without any interposed filters 15 20 min watchdog symbol parameter conditions min typ max unit t w(wdg) watchdog time-out duration 12,288 786,432 t cpu f cpu =8mhz 1.54 98.3 ms t wdgrst watchdog reset pulse width 500 ns motor control symbol parameter conditions min typ 1) max unit v offset comparator offset error <10 100 mv v mtchyst mcia/b/c comparator hysteresis 2) 35 80 130 mv t propag comparator propagation delay 1 m s reference voltage tolerance 5 % r1 v cref resistance bridge 30 k w r2 70 0.7 da / aa tolerance 5% d v ref v ref a = r1+r2 r2 t comparator ideal comparator output real v in t propag t propag v offset v offset v ref + v mtchyst 2 v ref - v mtchyst 2
st72141k 123/132 memory and peripheral characteristics (contd) figure 65. spi master timing diagram cpha=0, cpol=0 2) notes: 1) data based on characterization results, not tested in production. 2) measurement points are v ol , v oh , v il and v ih in the spi timing diagram spi serial peripheral interface ref. symbol parameter condition value 1) unit min max f spi spi frequency master slave 1/128 dc 1/4 1/2 f cpu 1t spi spi clock period master slave 4 2 t cpu 2t lead enable lead time slave 120 ns 3t lag enable lag time slave 120 ns 4t spi_h clock (sck) high time master slave 100 90 ns 5t spi_l clock (sck) low time master slave 100 90 ns 6t su data set-up time master slave 100 100 ns 7t h data hold time (inputs) master slave 100 100 ns 8t a access time (time to data active from high impedance state) slave 0 120 ns 9t dis disable time (hold time to high im- pedance state) 240 ns 10 t v data valid master (before capture edge) slave (after enable edge) 0.25 120 t cpu ns 11 t hold data hold time (outputs) master (before capture edge) slave (after enable edge) 0.25 0 t cpu ns 12 t rise rise time (20% v dd to 70% v dd , c l = 200pf) outputs: sck,mosi,miso inputs: sck,mosi,miso,ss 100 100 ns m s 13 t fall fall time (70% v dd to 20% v dd , c l = 200pf) outputs: sck,mosi,miso inputs: sck,mosi,miso,ss 100 100 ns m s 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 d7-out d6-out d0-out d7-in d6-in d0-in vr000109
st72141k 124/132 memory and peripheral characteristics (contd) figure 66. spi master timing diagram cpha=0, cpol=1 1) figure 67. spi master timing diagram cpha=1, cpol=0 1) figure 68. spi master timing diagram cpha=1, cpol=1 1) note: 1) measurement points are v ol , v oh , v il and v ih in the spi timing diagram 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 vr000110 d7-out d6-out d0-out d7-in d6-in d0-in 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 5 4 vr000107 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 vr000108 d7-out d6-out d0-out d7-in d6-in d0-in
st72141k 125/132 memory and peripheral characteristics (contd) measurement points are v ol , v oh , v il and v ih in the spi timing diagram figure 69. spi slave timing diagram cpha=0, cpol=0 1) figure 70. spi slave timing diagram cpha=0, cpol=1 1) figure 71. spi slave timing diagram cpha=1, cpol=0 1) figure 72. spi slave timing diagram cpha=1, cpol=1 1) note: 1) measurement points are v ol , v oh , v il and v ih in the spi timing diagram 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000113 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000114 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000111 d7-out d6-out d0-out d7-in d6-in d0-in 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 54 (input) 2 3 8 9 high-z d7-out d6-out d0-out d7-in d6-in d0-in vr000112
st72141k 126/132 memory and peripheral characteristics (contd) notes: 1) unless otherwise specified, typical data is based on t a =25c and v dd -v ss =5v. this data is provided only for design guidelines and is not tested. 2) tested in production at t a =25c, characterized over all temperature range. 3) adc accuracy vs. negative injection current: for i inj- =0.8ma, the typical leakage induced inside the die is 1.6 m a and the effect on the adc accuracy is a loss of 1 lsb by 10k w increase of the external analog source impedance. these measurement results and recommendations have been done under worst conditions for injection: - negative injection - injection to an input with analog capability, adjacent to the enabled analog input - at 5v v dd supply, and worst case temperature. 4) data based on characterization results, not tested in production. adc analog to digital converter (8-bit) symbol parameter conditions min typ 1) max unit |tue| total unadjusted error 3) t a =25c,v dd =v dda =5v, 2) f cpu =8mhz 2 lsb oe offset error 3) -1 1 ge gain error 3) -2 2 |dle| differential linearity error 3) 1 |ile| integral linearity error 3) 2 v ain conversion range voltage v ssa v dda v i adc a/d conversion supply current f adc =f cpu =4mhz v dd =v dda =5v 1ma t stab stabilization time after adc enable 30 m s t load sample capacitor loading time 8 32 m s 1/f adc t conv hold conversion time 8 32 m s 1/f adc r ain external input resistor 20 4) k w r adc internal input resistor 18 k w c sample sample capacitor 22 pf
st72141k 127/132 memory and peripheral characteristics (contd) px.x/ainx r ain v ain c pin 5pf v dd v t = 0.6v leakage v t = 0.6v c pin v t leakage c hold ss sampling switch ss r ss at the pin due to various junctions c hold 6 pf capacitance = input capacitance = threshold voltage = sampling switch = sample/hold 1a v ss = leakage current 2 kw oe ge 1 lsb (ideal) 1lsb ideal v dda v ssa C 256 ---------------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line tue =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. oe =offset error: deviation between the first actual transition and the first ideal one. ge =gain error: deviation between the last ideal transition and the last actual one. dle =differential linearity error: maximum devia- tion between actual steps and the ideal one. ile =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 255 254 253 5 4 3 2 1 0 7 6 1234567 253 254 255 256 (1) (2) tue dle ile (3) v dda v ssa
st72141k 128/132 11 general information 11.1 package mechanical data figure 73. 32-pin plastic dual in-line package, shrink 400-mil width figure 74. 34-pin plastic small outline package, shrink 300-mil width dim. mm inches min typ max min typ max a 3.56 3.76 5.08 0.140 0.148 0.200 a1 0.51 0.020 a2 3.05 3.56 4.57 0.120 0.140 0.180 b 0.36 0.46 0.58 0.014 0.018 0.023 b1 0.76 1.02 1.40 0.030 0.040 0.055 c 0.20 0.25 0.36 0.008 0.010 0.014 d 27.43 28.45 1.080 1.100 1.120 e 9.91 10.41 11.05 0.390 0.410 0.435 e1 7.62 8.89 9.40 0.300 0.350 0.370 e 1.78 0.070 ea 10.16 0.400 eb 12.70 0.500 ec 1.40 0.055 l 2.54 3.05 3.81 0.100 0.120 0.150 number of pins n 32 d b2 b e a a1 a2 l e1 e ec c ea eb dim. mm inches min typ max min typ max a 2.464 2.642 0.097 0.104 a1 0.127 0.292 0.005 0.012 b 0.356 0.483 0.014 0.019 c 0.231 0.318 0.009 0.013 d 17.72 9 18.05 9 0.698 0.711 e 7.417 7.595 0.292 0.299 e 1.016 0.040 h 10.16 0 10.41 4 0.400 0.410 h 0.635 0.737 0.025 0.029 a 0 8 0 8 l 0.610 1.016 0.024 0.040 number of pins n 34 h x 45 c l a a a1 e b d h e
st72141k 129/132 11.2 ordering information transfer of customer code customer code is made up of the rom contents and the list of the selected options (if any). the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file gener- ated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to stmi- croelectronics using the correctly completed op- tion list appended. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. figure 75. rom factory coded device types figure 76. otp user programmable device types device package temp. range xxx / code name (defined by stmicroelectronics) 6= industrial -40 to +85 c 3= automotive -40 to +125 c b= plastic dip m= plastic soic st72141k2 device package temp. range code name (defined by stmicroelectronics) 6= industrial -40 to +85 c 3= automotive -40 to +125 c b= plastic dip m= plastic soic ST72T141K2 xxx
st72141k 130/132 microcontroller option list customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . stmicroelectronics references device: [ ] st72141k2 package: [ ] so34 [ ] sdip32 conditioning: [ ] tube [ ] tape & reel (not available for sdip packages) temperature range: [ ] -40 to 85c [ ] -40 to 125c readout protection: [ ] enabled [ ] disabled special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _" authorized characters are letters, digits, '.', '-', '/' and spaces only. maximum character count: dip32 10 so34 13 comments : notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
st72141k 131/132 12 summary of changes description of the changes between the current release of the specification and the previous one. rev. main changes date 1.8 added vtpor in section 10.6.1 on page 121 modified vmtchyst and voffset in section 10.7 on page 122 modified option list in section 11.2 oct 01
st72141k 132/132 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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